ShiboSoftwareDev/am625sip-linux-board
This code defines the physical footprint and pin layout for an AM625 System-in-Package (SIP) component, detailing pad positions, pin labels, and package outline for hardware integration.
- Version
- 1.0.24
- License
- unset
- Stars
- 0
index.circuit.tsx
PCB
Schematic
import { AM625SIP_BALLS, Am625Sip } from "./components/am625sip"
import { X322525MOB4SI } from "./imports/X322525MOB4SI"
import { Fragment } from "react"
import hdmiCircuitJson from "./subcircuits/cache/hdmi.circuit.json"
import microSdCircuitJson from "./subcircuits/cache/microsd.circuit.json"
import capVddsCircuitJson from "./subcircuits/cache/cap-vdds.circuit.json"
import pmicVsysCircuitJson from "./subcircuits/cache/pmic-vsys.circuit.json"
import usbCDeviceCircuitJson from "./subcircuits/cache/usb-c-device.circuit.json"
import usb0AnalogSupportCircuitJson from "./subcircuits/cache/usb0-analog-support.circuit.json"
import usb0DataEsdCircuitJson from "./subcircuits/cache/usb0-data-esd.circuit.json"
import { CAP_VDDS_LINKS } from "./subcircuits/cap-vdds"
import { PowerInputSubcircuit } from "./subcircuits/power-input"
import { MICROSD_SOC_BOUNDARY_Y } from "./subcircuits/microsd"
import { createCachedSocFanoutAutorouter } from "./subcircuits/cached-soc-fanout-autorouter"
const SIGNAL_LAYERS = ["top", "inner1", "inner2", "bottom"] as const
const ANALOG_ROUTE_PHASE_COUNT = 24
const PMIC_INPUT_ROUTE_PHASE_COUNT = 10
const PMIC_LDO2_ROUTE_PHASES = {
LOCAL: 22.1,
ISOLATION: 22.11,
FEED: 22.12,
} as const
const VOUT_ROUTE_PHASE_BASE = 22.7
const VOUT_ROUTE_PHASE = {
PCLK: VOUT_ROUTE_PHASE_BASE,
DE: VOUT_ROUTE_PHASE_BASE + 0.1,
HSYNC: VOUT_ROUTE_PHASE_BASE + 0.2,
VSYNC_LOCAL: VOUT_ROUTE_PHASE_BASE + 0.24,
VSYNC: VOUT_ROUTE_PHASE_BASE + 0.25,
} as const
const POWER_INPUT_VSYS_ROUTE_PHASE = 22.6
const UART0_ESCAPE_PHASE = {
RX: 22.48,
TX: 22.49,
} as const
const UART0_HEADER_GROUND_PHASE = 22.5
const UART0_ROUTE_PHASE = {
RX: 22.51,
TX: 22.52,
} as const
const PMIC_RESET_ROUTE_PHASE = {
SIGNAL: 29.1,
PULLUP_SIGNAL: 29.11,
PULLUP_SUPPLY: 29.12,
} as const
const PMIC_LPM_ROUTE_PHASE = {
SIGNAL: 29.2,
PMIC_LINK: 29.21,
PULLUP_SUPPLY: 29.22,
} as const
const PMIC_INTERRUPT_ROUTE_PHASE = {
SIGNAL: 29.3,
PMIC_LINK: 29.31,
PULLUP_SUPPLY: 29.32,
} as const
const USB0_ESCAPE_PHASE = 22.53
const USB0_ANALOG_PHASE = {
SOC_LINKS: 22.54,
CONNECTOR_VBUS: 22.56,
GROUND: 22.58,
} as const
const USB0_CONNECTOR_PHASE = {
DATA_TO_ESD: 22.55,
DATA_TO_CONNECTOR: 22.551,
ESD_GROUND: 22.552,
GND: 22.57,
} as const
const ANALOG_ROUTE_REGION = {
shape: "rect" as const,
minX: -14,
maxX: 14.5,
minY: -19,
maxY: 22.5,
}
const getAnalogRoutePhase = (index: number) =>
Number((17 + index / 100).toFixed(2))
const getPmicInputRoutePhase = (index: number) =>
Number((21.2 + index / 100).toFixed(2))
interface SocBreakoutBus {
name: string
preferredLayers: (typeof SIGNAL_LAYERS)[number][]
points: Array<{
ball: string
pcbX: number
pcbY: number
}>
}
const SOC_BREAKOUT_BUSES: SocBreakoutBus[] = [
{
name: "MCU_OSC0",
preferredLayers: ["inner2"],
points: [
{ ball: "B2", pcbX: -9.5, pcbY: 9.9999 },
{ ball: "A3", pcbX: -8.5, pcbY: 9.9999 },
],
},
{
name: "WKUP_LFOSC0",
preferredLayers: ["top"],
points: [
{ ball: "C1", pcbX: -9, pcbY: 11.9999 },
{ ball: "C2", pcbX: -8, pcbY: 11.9999 },
],
},
{
name: "PMIC_CONTROL",
preferredLayers: ["bottom"],
points: [
{ ball: "D2", pcbX: 6.25, pcbY: 9.9999 },
{ ball: "B7", pcbX: 7.25, pcbY: 9.9999 },
{ ball: "A16", pcbX: 8.25, pcbY: 9.9999 },
{ ball: "B16", pcbX: 9.25, pcbY: 9.9999 },
{ ball: "D16", pcbX: 9.9999, pcbY: 8.5 },
],
},
{
name: "JTAG_DEBUG",
preferredLayers: ["top", "inner1"],
points: [
{ ball: "A10", pcbX: -2, pcbY: 11.9999 },
{ ball: "B10", pcbX: -1.5, pcbY: 11.9999 },
{ ball: "A11", pcbX: -1, pcbY: 11.9999 },
{ ball: "B11", pcbX: -0.5, pcbY: 11.9999 },
{ ball: "C11", pcbX: 0, pcbY: 11.9999 },
{ ball: "D12", pcbX: 0.5, pcbY: 11.9999 },
{ ball: "E12", pcbX: 1, pcbY: 11.9999 },
],
},
{
name: "UART0_CONSOLE",
preferredLayers: ["inner1"],
points: [
{ ball: "D14", pcbX: 13, pcbY: 11 },
{ ball: "E14", pcbX: 13, pcbY: 12 },
],
},
{
name: "MMC1_MICROSD",
preferredLayers: ["inner1"],
points: [
{ ball: "A21", pcbX: 9.9999, pcbY: 9 },
{ ball: "A22", pcbX: 9.9999, pcbY: 8 },
{ ball: "B21", pcbX: 9.9999, pcbY: 7 },
{ ball: "B22", pcbX: 9.9999, pcbY: 6 },
{ ball: "C21", pcbX: 9.9999, pcbY: 5 },
{ ball: "D22", pcbX: 9.9999, pcbY: 4 },
{ ball: "C17", pcbX: 9.9999, pcbY: 3 },
{ ball: "D17", pcbX: 9.9999, pcbY: 2 },
],
},
{
name: "USB0_DATA",
preferredLayers: ["inner2"],
points: [
{ ball: "AD11", pcbX: 2.75, pcbY: -9.9999 },
{ ball: "AE11", pcbX: 3.25, pcbY: -9.9999 },
],
},
{
name: "USB0_ANALOG",
preferredLayers: ["bottom"],
points: [
{ ball: "AE10", pcbX: 1.25, pcbY: -9.9999 },
{ ball: "AC11", pcbX: 1.75, pcbY: -9.9999 },
],
},
]
const getSocBus = (name: string) =>
SOC_BREAKOUT_BUSES.find((bus) => bus.name === name)!
const MCU_OSC0_BUS = getSocBus("MCU_OSC0")
const UART0_CONSOLE_BUS = getSocBus("UART0_CONSOLE")
const USB0_DATA_BUS = getSocBus("USB0_DATA")
const USB0_ANALOG_BUS = getSocBus("USB0_ANALOG")
const PMIC_CONTROL_BUS = getSocBus("PMIC_CONTROL")
const PMIC_RUNTIME_BUS: SocBreakoutBus = {
...PMIC_CONTROL_BUS,
points: [
PMIC_CONTROL_BUS.points[2]!,
PMIC_CONTROL_BUS.points[3]!,
PMIC_CONTROL_BUS.points[0]!,
PMIC_CONTROL_BUS.points[1]!,
],
}
const MMC1_MICROSD_BUS = getSocBus("MMC1_MICROSD")
const MMC1_BOOT_BUS: SocBreakoutBus = {
...MMC1_MICROSD_BUS,
points: [
{
...MMC1_MICROSD_BUS.points[0]!,
pcbX: 20,
pcbY: MICROSD_SOC_BOUNDARY_Y.CMD,
},
{
...MMC1_MICROSD_BUS.points[1]!,
pcbX: 20,
pcbY: MICROSD_SOC_BOUNDARY_Y.DAT0,
},
{
...MMC1_MICROSD_BUS.points[3]!,
pcbX: 20,
pcbY: MICROSD_SOC_BOUNDARY_Y.CLK,
},
],
}
const MMC1_BOOT_CONNECTIONS = [
{ ball: "A21", pin: "CMD" },
{ ball: "A22", pin: "DAT0" },
{ ball: "B22", pin: "CLK" },
] as const
const SOC_IO_1P8_BUSES: SocBreakoutBus[] = [
{
name: "SOC_IO_1P8_TOP",
preferredLayers: [...SIGNAL_LAYERS],
points: [
{ ball: "G7", pcbX: -7.5, pcbY: 9.9999 },
{ ball: "H9", pcbX: -6.5, pcbY: 9.9999 },
{ ball: "F11", pcbX: -5.5, pcbY: 9.9999 },
{ ball: "G12", pcbX: -4.5, pcbY: 9.9999 },
{ ball: "G14", pcbX: -3.5, pcbY: 9.9999 },
{ ball: "F15", pcbX: -2.5, pcbY: 9.9999 },
{ ball: "G17", pcbX: -1.5, pcbY: 9.9999 },
],
},
{
name: "SOC_IO_1P8_RIGHT",
preferredLayers: [...SIGNAL_LAYERS],
points: [
{ ball: "J18", pcbX: 9.9999, pcbY: 5 },
{ ball: "L18", pcbX: 9.9999, pcbY: 1.5 },
{ ball: "M19", pcbX: 9.9999, pcbY: 3 },
{ ball: "N18", pcbX: 4, pcbY: -9.9999 },
{ ball: "P18", pcbX: 7, pcbY: -9.9999 },
{ ball: "T19", pcbX: 8.5, pcbY: -9.9999 },
],
},
{
name: "SOC_IO_1P8_LEFT",
preferredLayers: [...SIGNAL_LAYERS],
points: [
{ ball: "M4", pcbX: -9.9999, pcbY: 1 },
{ ball: "N3", pcbX: -9.9999, pcbY: 0 },
],
},
{
name: "SOC_IO_1P8_BOTTOM",
preferredLayers: [...SIGNAL_LAYERS],
points: [
{ ball: "T7", pcbX: -1, pcbY: -9.9999 },
{ ball: "U18", pcbX: 9, pcbY: -9.9999 },
{ ball: "W16", pcbX: 6.5, pcbY: -9.9999 },
{ ball: "W19", pcbX: 8, pcbY: -9.9999 },
],
},
]
const SOC_IO_1P8_FANOUT_PAIR_BUSES = [
{
name: "SOC_IO_1P8_RIGHT_LOWER_PAIR",
balls: ["N18", "T19"],
preferredLayers: ["inner1"],
},
{
name: "SOC_IO_1P8_BOTTOM_RIGHT_PAIR",
balls: ["U18", "W19"],
preferredLayers: ["bottom"],
},
] as const
/**
* Preserve the layer assignment from the proven 205-connection SoC fanout.
* Without these explicit buses, adding one unrelated escape can rebalance
* single-ball supply routes and invalidate already-routed parent phases.
*/
const SOC_IO_1P8_PINNED_FANOUT_BUSES = [
{ name: "SOC_IO_1P8_G7_PINNED", balls: ["G7"], preferredLayers: ["bottom"] },
{ name: "SOC_IO_1P8_H9_PINNED", balls: ["H9"], preferredLayers: ["inner1"] },
{ name: "SOC_IO_1P8_F11_PINNED", balls: ["F11"], preferredLayers: ["inner2"] },
{ name: "SOC_IO_1P8_G12_PINNED", balls: ["G12"], preferredLayers: ["bottom"] },
{ name: "SOC_IO_1P8_G14_PINNED", balls: ["G14"], preferredLayers: ["inner1"] },
{ name: "SOC_IO_1P8_F15_PINNED", balls: ["F15"], preferredLayers: ["inner2"] },
{ name: "SOC_IO_1P8_G17_PINNED", balls: ["G17"], preferredLayers: ["bottom"] },
{ name: "SOC_IO_1P8_J18_PINNED", balls: ["J18"], preferredLayers: ["bottom"] },
{ name: "SOC_IO_1P8_L18_PINNED", balls: ["L18"], preferredLayers: ["inner2"] },
{ name: "SOC_IO_1P8_M19_PINNED", balls: ["M19"], preferredLayers: ["bottom"] },
{ name: "SOC_IO_1P8_P18_PINNED", balls: ["P18"], preferredLayers: ["inner1"] },
{ name: "SOC_IO_1P8_M4_PINNED", balls: ["M4"], preferredLayers: ["inner2"] },
{ name: "SOC_IO_1P8_N3_PINNED", balls: ["N3"], preferredLayers: ["bottom"] },
{ name: "SOC_IO_1P8_T7_PINNED", balls: ["T7"], preferredLayers: ["inner1"] },
{ name: "SOC_IO_1P8_W16_PINNED", balls: ["W16"], preferredLayers: ["inner2"] },
] as const
const SOC_IO_1P8_FANOUT_BUSES = [
...SOC_IO_1P8_FANOUT_PAIR_BUSES,
...SOC_IO_1P8_PINNED_FANOUT_BUSES,
] as const
const DDR_STRAPS_BUS: SocBreakoutBus = {
name: "DDR_STRAPS",
preferredLayers: ["inner1"],
points: [
{ ball: "G1", pcbX: -9.9999, pcbY: 6 },
{ ball: "M2", pcbX: -9.9999, pcbY: -3 },
{ ball: "R3", pcbX: -9.9999, pcbY: -6 },
],
}
const CAP_VDDS_BREAKOUT_BUSES: SocBreakoutBus[] = [
{
name: "CAP_VDDS_TOP",
preferredLayers: ["inner2"],
points: CAP_VDDS_LINKS.slice(0, 4).map(
({ ball, exitX, exitY }) => ({
ball,
pcbX: exitX,
pcbY: exitY,
}),
),
},
{
name: "CAP_VDDS_RIGHT",
preferredLayers: ["inner1"],
points: CAP_VDDS_LINKS.slice(4, 7).map(
({ ball, exitX, exitY }) => ({
ball,
pcbX: exitX,
pcbY: exitY,
}),
),
},
{
name: "CAP_VDDS_BOTTOM",
preferredLayers: ["bottom"],
points: CAP_VDDS_LINKS.slice(7, 9).map(
({ ball, exitX, exitY }) => ({
ball,
pcbX: exitX,
pcbY: exitY,
}),
),
},
]
const VOUT_CONTROL_CONNECTIONS = [
{ name: "VOUT0_PCLK", ball: "AC24", pin: "IDCK_P", pcbX: 8, pcbY: -12.9999, routingPhase: VOUT_ROUTE_PHASE.PCLK },
{ name: "VOUT0_DE", ball: "Y20", pin: "DE", pcbX: 6, pcbY: -12.9999, routingPhase: VOUT_ROUTE_PHASE.DE },
{ name: "VOUT0_HSYNC", ball: "AB24", pin: "HSYNC", pcbX: 7, pcbY: -12.9999, routingPhase: VOUT_ROUTE_PHASE.HSYNC },
{ name: "VOUT0_VSYNC", ball: "AC25", pin: "VSYNC", pcbX: 9, pcbY: -12.9999, routingPhase: VOUT_ROUTE_PHASE.VSYNC },
] as const
// Add the control bus incrementally so each new BGA escape is validated.
const ACTIVE_VOUT_CONTROL_CONNECTIONS = VOUT_CONTROL_CONNECTIONS.slice(0, 4)
const VOUT_CONTROL_FAST_BUS: SocBreakoutBus = {
name: "VOUT_CONTROL_FAST",
preferredLayers: ["inner2"],
points: ACTIVE_VOUT_CONTROL_CONNECTIONS.slice(0, 2).map(
({ ball, pcbX, pcbY }) => ({ ball, pcbX, pcbY }),
),
}
const VOUT_HSYNC_ESCAPE_BUS: SocBreakoutBus = {
name: "VOUT_HSYNC_ESCAPE",
preferredLayers: ["inner1"],
points: ACTIVE_VOUT_CONTROL_CONNECTIONS.slice(2).map(
({ ball, pcbX, pcbY }) => ({ ball, pcbX, pcbY }),
),
}
const SOC_ANALOG_1P8_BUSES: SocBreakoutBus[] = [
{
name: "SOC_ANALOG_1P8_TOP",
preferredLayers: [...SIGNAL_LAYERS],
points: [
{ ball: "G16", pcbX: 13, pcbY: 7.5 },
{ ball: "L11", pcbX: 5.25, pcbY: 9.9999 },
],
},
{
name: "SOC_ANALOG_1P8_RIGHT",
preferredLayers: [...SIGNAL_LAYERS],
points: [{ ball: "L14", pcbX: 9.9999, pcbY: -5 }],
},
{
name: "SOC_ANALOG_1P8_BOTTOM",
preferredLayers: [...SIGNAL_LAYERS],
points: [
{ ball: "T9", pcbX: -9, pcbY: -9.9999 },
{ ball: "U11", pcbX: -8, pcbY: -9.9999 },
{ ball: "U15", pcbX: -7, pcbY: -9.9999 },
{ ball: "W9", pcbX: -6, pcbY: -9.9999 },
{ ball: "W10", pcbX: -5, pcbY: -9.9999 },
{ ball: "W14", pcbX: -4, pcbY: -9.9999 },
{ ball: "Y11", pcbX: -1, pcbY: -9.9999 },
],
},
]
const SOC_ANALOG_1P8_PINNED_FANOUT_BUSES = [
{ name: "SOC_ANALOG_1P8_G16_PINNED", balls: ["G16"], preferredLayers: ["bottom"] },
{ name: "SOC_ANALOG_1P8_L11_PINNED", balls: ["L11"], preferredLayers: ["bottom"] },
{ name: "SOC_ANALOG_1P8_L14_PINNED", balls: ["L14"], preferredLayers: ["inner1"] },
{ name: "SOC_ANALOG_1P8_T9_PINNED", balls: ["T9"], preferredLayers: ["inner2"] },
{ name: "SOC_ANALOG_1P8_U11_PINNED", balls: ["U11"], preferredLayers: ["bottom"] },
{ name: "SOC_ANALOG_1P8_U15_PINNED", balls: ["U15"], preferredLayers: ["inner1"] },
{ name: "SOC_ANALOG_1P8_W9_PINNED", balls: ["W9"], preferredLayers: ["inner2"] },
{ name: "SOC_ANALOG_1P8_W10_PINNED", balls: ["W10"], preferredLayers: ["bottom"] },
{ name: "SOC_ANALOG_1P8_W14_PINNED", balls: ["W14"], preferredLayers: ["inner1"] },
{ name: "SOC_ANALOG_1P8_Y11_PINNED", balls: ["Y11"], preferredLayers: ["inner2"] },
] as const
const ACTIVE_BREAKOUT_BUSES = [
MCU_OSC0_BUS,
PMIC_RUNTIME_BUS,
MMC1_BOOT_BUS,
...SOC_IO_1P8_BUSES,
DDR_STRAPS_BUS,
...SOC_ANALOG_1P8_BUSES,
...CAP_VDDS_BREAKOUT_BUSES,
VOUT_CONTROL_FAST_BUS,
VOUT_HSYNC_ESCAPE_BUS,
UART0_CONSOLE_BUS,
USB0_DATA_BUS,
USB0_ANALOG_BUS,
]
const SOC_GROUND_BALLS = [
...AM625SIP_BALLS.filter(([, signalName]) => signalName === "VSS").map(
([ballName]) => ballName,
),
"C2", // Ground WKUP_LFOSC0_XI when the optional 32.768 kHz crystal is omitted.
]
const SOC_CORE_BALLS = AM625SIP_BALLS.filter(([, signalName]) =>
[
"VDD_CORE",
"VDDR_CORE",
"VDD_CANUART",
"VDDA_CORE_USB",
"VDDA_CORE_CSIRX0",
].includes(signalName),
).map(([ballName]) => ballName)
const SOC_DDR_1P1_BALLS = AM625SIP_BALLS.filter(([, signalName]) =>
["VDDS_MEM_1P1", "VDDS_DDR"].includes(signalName),
).map(([ballName]) => ballName)
const SOC_BUS_DIRECTIONS = {
MCU_OSC0: "topside_left",
WKUP_LFOSC0: "topside_left",
PMIC_CONTROL: "topside_right",
JTAG_DEBUG: "topside_center",
UART0_CONSOLE: "rightside_top",
MMC1_MICROSD: "rightside_top",
USB0_DATA: "bottomside_center",
USB0_ANALOG: "bottomside_center",
SOC_IO_1P8_TOP: "topside_center",
SOC_IO_1P8_RIGHT: "rightside_center",
SOC_IO_1P8_LEFT: "leftside_center",
SOC_IO_1P8_BOTTOM: "bottomside_center",
DDR_STRAPS: "leftside_center",
VOUT_CONTROL_FAST: "bottomside_right",
VOUT_HSYNC_ESCAPE: "bottomside_right",
SOC_IO_1P8_RIGHT_LOWER_PAIR: "bottomside_center",
SOC_IO_1P8_BOTTOM_RIGHT_PAIR: "bottomside_right",
} as const
const ACTIVE_BUS_DIRECTIONS = {
MCU_OSC0: SOC_BUS_DIRECTIONS.MCU_OSC0,
PMIC_CONTROL: SOC_BUS_DIRECTIONS.PMIC_CONTROL,
MMC1_MICROSD: SOC_BUS_DIRECTIONS.MMC1_MICROSD,
DDR_STRAPS: SOC_BUS_DIRECTIONS.DDR_STRAPS,
VOUT_CONTROL_FAST: SOC_BUS_DIRECTIONS.VOUT_CONTROL_FAST,
VOUT_HSYNC_ESCAPE: SOC_BUS_DIRECTIONS.VOUT_HSYNC_ESCAPE,
SOC_IO_1P8_RIGHT_LOWER_PAIR:
SOC_BUS_DIRECTIONS.SOC_IO_1P8_RIGHT_LOWER_PAIR,
SOC_IO_1P8_BOTTOM_RIGHT_PAIR:
SOC_BUS_DIRECTIONS.SOC_IO_1P8_BOTTOM_RIGHT_PAIR,
UART0_ESCAPE: SOC_BUS_DIRECTIONS.UART0_CONSOLE,
USB0_DATA: SOC_BUS_DIRECTIONS.USB0_DATA,
USB0_ANALOG: SOC_BUS_DIRECTIONS.USB0_ANALOG,
PMIC_RESET_SOC_BUS: "topside_center",
PMIC_LPM_SOC_BUS: "topside_center",
PMIC_INTERRUPT_SOC_BUS: "topside_center",
} as const
export default () => (
<board
name="POCKET_SITARA_REV_A"
width="140mm"
height="70mm"
layers={4}
defaultTraceWidth="0.08128mm"
minTraceWidth="0.08128mm"
minTraceToPadEdgeClearance="0.05mm"
minPadEdgeToPadEdgeClearance="0.08128mm"
minViaEdgeToPadEdgeClearance="0.08128mm"
minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
minViaHoleDiameter="0.1mm"
minViaPadDiameter="0.24mm"
pcbStyle={{
viaHoleDiameter: "0.1mm",
viaPadDiameter: "0.24mm",
}}
autorouter="default"
schematicDisabled
>
<autoroutingphase
name="OSC_GROUND_PLANE_DROPS"
phaseIndex={0}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="PMIC_GROUND_PLANE_DROPS"
phaseIndex={1}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
busFanoutDirections={{ PMIC_AGND_DROP: "center_left" }}
region={{ shape: "rect", minX: 7, maxX: 12, minY: 17, maxY: 23 }}
/>
<autoroutingphase
name="PMIC_GROUND_TIE"
phaseIndex={1.005}
autorouter="default"
region={{ shape: "rect", minX: 6.5, maxX: 10, minY: 19, maxY: 23 }}
/>
<autoroutingphase
name="PMIC_C3_GROUND_DROP"
phaseIndex={1.01}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 18, maxX: 19, minY: 26.5, maxY: 27.5 }}
/>
<autoroutingphase
name="PMIC_C4_GROUND_DROP"
phaseIndex={1.011}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 12, maxX: 13, minY: 15.5, maxY: 16.5 }}
/>
<autoroutingphase
name="PMIC_C5_GROUND_DROP"
phaseIndex={1.012}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 6.5, maxX: 7.5, minY: 14.8, maxY: 15.8 }}
/>
<autoroutingphase
name="PMIC_ANALOG_CAP_GROUND_DROPS"
phaseIndex={1.02}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 7, maxX: 9, minY: 22.5, maxY: 25.5 }}
/>
<autoroutingphase
name="PMIC_LDO_GROUND_DROPS"
phaseIndex={1.1}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 3.5, maxX: 25, minY: 17, maxY: 24 }}
/>
<autoroutingphase
name="PMIC_BUCK1_GROUND_DROPS"
phaseIndex={1.2}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 20.5, maxX: 22.5, minY: 16, maxY: 21 }}
/>
<autoroutingphase
name="PMIC_BUCK2_GROUND_DROPS"
phaseIndex={1.3}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 17, maxX: 19, minY: 15, maxY: 20 }}
/>
<autoroutingphase
name="PMIC_BUCK3_GROUND_DROPS"
phaseIndex={1.4}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: -1, maxX: 1, minY: 15, maxY: 20 }}
/>
<autoroutingphase
name="MICROSD_GROUND_PLANE_DROPS"
phaseIndex={2}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="CORE_POWER_PLANE_DROPS"
phaseIndex={3}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{
inner1: ["GND"],
inner2: ["VDD_CORE_0V85"],
}}
/>
<autoroutingphase
name="DDR_POWER_PLANE_DROPS"
phaseIndex={4}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{
inner1: ["GND"],
bottom: ["VDD_DDR_1V1"],
}}
/>
<autoroutingphase
name="DDR_HF_POWER_PLANE_DROPS"
phaseIndex={5}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{
inner1: ["GND"],
bottom: ["VDD_DDR_1V1"],
}}
/>
<autoroutingphase
name="DDR_BULK_C33_PLANE_DROPS"
phaseIndex={6}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"], bottom: ["VDD_DDR_1V1"] }}
/>
<autoroutingphase
name="DDR_BULK_C34_PLANE_DROPS"
phaseIndex={7}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"], bottom: ["VDD_DDR_1V1"] }}
/>
<autoroutingphase
name="DDR_BULK_C35_PLANE_DROPS"
phaseIndex={8}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"], bottom: ["VDD_DDR_1V1"] }}
/>
<autoroutingphase
name="DDR_HF_RIGHT_PLANE_DROPS"
phaseIndex={9}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"], bottom: ["VDD_DDR_1V1"] }}
/>
<autoroutingphase
name="DDR_STRAP_GROUND_DROPS"
phaseIndex={10}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="DDR_ZQ_POWER_DROP"
phaseIndex={11}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ bottom: ["VDD_DDR_1V1"] }}
/>
<autoroutingphase
name="ANALOG_C42_GROUND_DROP"
phaseIndex={12}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="ANALOG_C43_GROUND_DROP"
phaseIndex={12.1}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="CAP_VDDS_TOP_LEFT_GROUND_DROPS"
phaseIndex={13}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="CAP_VDDS_TOP_RIGHT_GROUND_DROPS"
phaseIndex={14}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="CAP_VDDS_REMAINING_GROUND_DROPS"
phaseIndex={15}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="HDMI_LOCAL_GROUND_DROPS"
phaseIndex={16}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="HDMI_LOCAL_SIGNAL_ROUTES"
phaseIndex={18}
autorouter="default"
/>
{Array.from({ length: ANALOG_ROUTE_PHASE_COUNT }, (_, index) => (
<Fragment key={`ANALOG_1V8_LINK_${index + 1}`}>
<autoroutingphase
name={`ANALOG_1V8_LINK_${index + 1}`}
phaseIndex={getAnalogRoutePhase(index)}
autorouter="default"
region={ANALOG_ROUTE_REGION}
/>
</Fragment>
))}
<autoroutingphase
name="ANALOG_1V8_LOCAL_NET"
phaseIndex={17.3}
autorouter="default"
region={ANALOG_ROUTE_REGION}
/>
<autoroutingphase
name="HDMI_LOCAL_POWER_ROUTES"
phaseIndex={20}
autorouter="default"
/>
<autoroutingphase
name="MICROSD_SIGNAL_ROUTES"
phaseIndex={21}
autorouter="default"
region={{
shape: "rect",
minX: 18.5,
maxX: 21.2,
minY: 2.7,
maxY: 10.2,
}}
/>
<autoroutingphase
name="PMIC_BUCK1_POWER_ROUTES"
phaseIndex={22}
autorouter="default"
region={{ shape: "rect", minX: 8, maxX: 22.5, minY: 16.9, maxY: 21.5 }}
/>
<autoroutingphase
name="PMIC_BUCK2_BUCK3_POWER_ROUTES"
phaseIndex={22.05}
autorouter="default"
region={{ shape: "rect", minX: -1, maxX: 21, minY: 13, maxY: 21 }}
/>
<autoroutingphase
name="VDD_IO_1V8_ROUTES"
phaseIndex={23}
autorouter="default"
region={{ shape: "rect", minX: -13, maxX: 22, minY: -14, maxY: 22 }}
/>
{Array.from({ length: PMIC_INPUT_ROUTE_PHASE_COUNT }, (_, index) => (
<Fragment key={`PMIC_INPUT_ROUTE_${index + 1}`}>
<autoroutingphase
name={`PMIC_INPUT_ROUTE_${index + 1}`}
phaseIndex={getPmicInputRoutePhase(index)}
autorouter="default"
region={{
shape: "rect",
minX: 6,
maxX: 13.5,
minY: 12.5,
maxY: 26,
}}
/>
</Fragment>
))}
<autoroutingphase
name="PMIC_VDD_SD_LOCAL_ROUTE"
phaseIndex={21.4}
autorouter="default"
region={{ shape: "rect", minX: 10.5, maxX: 15, minY: 20, maxY: 23.5 }}
/>
<autoroutingphase
name="PMIC_LDO2_LOCAL_ROUTE"
phaseIndex={PMIC_LDO2_ROUTE_PHASES.LOCAL}
autorouter="default"
region={{ shape: "rect", minX: 4.5, maxX: 7.5, minY: 19.5, maxY: 24.5 }}
/>
<autoroutingphase
name="PMIC_LDO2_ISOLATION_ROUTE"
phaseIndex={PMIC_LDO2_ROUTE_PHASES.ISOLATION}
autorouter="default"
region={{ shape: "rect", minX: 4.5, maxX: 6.5, minY: 16.3, maxY: 24.5 }}
/>
<autoroutingphase
name="PMIC_LDO2_FEED_ROUTE"
phaseIndex={PMIC_LDO2_ROUTE_PHASES.FEED}
autorouter="default"
region={{ shape: "rect", minX: 4.5, maxX: 18.5, minY: 14.5, maxY: 17.5 }}
/>
<autoroutingphase
name="PMIC_LDO34_LOCAL_ROUTE"
phaseIndex={24.03}
autorouter="default"
region={{ shape: "rect", minX: 4, maxX: 7.5, minY: 18.5, maxY: 23 }}
/>
<autoroutingphase
name="PMIC_LDO34_FEED_ROUTE"
phaseIndex={24.04}
autorouter="default"
region={{ shape: "rect", minX: 1.5, maxX: 6.5, minY: 20.5, maxY: 24.5 }}
/>
<autoroutingphase
name="PMIC_VLDO4_LOCAL_ROUTE"
phaseIndex={24.05}
autorouter="default"
region={{ shape: "rect", minX: 3.5, maxX: 7.5, minY: 17.5, maxY: 19.5 }}
/>
<autoroutingphase
name="PMIC_ENABLE_ROUTE"
phaseIndex={24.1}
autorouter="default"
region={{ shape: "rect", minX: 5, maxX: 12, minY: 13.5, maxY: 20 }}
/>
<autoroutingphase
name="PMIC_VSEL_ROUTE"
phaseIndex={24.11}
autorouter="default"
region={{ shape: "rect", minX: 4.5, maxX: 12, minY: 17, maxY: 27.5 }}
/>
<autoroutingphase
name="PMIC_SDA_LOCAL_ROUTE"
phaseIndex={22.2}
autorouter="default"
region={{ shape: "rect", minX: 6.5, maxX: 14, minY: 11.5, maxY: 25.5 }}
/>
<autoroutingphase
name="PMIC_SCL_LOCAL_ROUTE"
phaseIndex={22.3}
autorouter="default"
region={{ shape: "rect", minX: 8, maxX: 18.5, minY: 11.5, maxY: 26 }}
/>
<autoroutingphase
name="PMIC_PULLUP_SUPPLY_ROUTES"
phaseIndex={24.4}
autorouter="default"
region={{ shape: "rect", minX: 12.5, maxX: 18.5, minY: 15, maxY: 26 }}
/>
<autoroutingphase
name="HDMI_POWER_FEEDS"
phaseIndex={24.5}
autorouter="default"
region={{
shape: "rect",
minX: -18,
maxX: 20,
minY: 12,
maxY: 29,
}}
/>
<autoroutingphase
name="MICROSD_CMD_ROUTES"
phaseIndex={25}
autorouter="default"
region={{
shape: "rect",
minX: 10.8,
maxX: 24.1,
minY: 10.9,
maxY: 23.1,
}}
/>
<autoroutingphase
name="MICROSD_GROUND_LINK"
phaseIndex={25.1}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{
shape: "rect",
minX: 15.5,
maxX: 16.9,
minY: -14.7,
maxY: -13.3,
}}
/>
<autoroutingphase
name="POWER_INPUT_GROUND_LINK"
phaseIndex={26.1}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="UART0_RX_ESCAPE"
phaseIndex={UART0_ESCAPE_PHASE.RX}
autorouter="default"
region={{ shape: "rect", minX: 18.5, maxX: 23, minY: 4.5, maxY: 7.5 }}
/>
<autoroutingphase
name="UART0_TX_ESCAPE"
phaseIndex={UART0_ESCAPE_PHASE.TX}
autorouter="default"
region={{ shape: "rect", minX: 18.5, maxX: 23.5, minY: 4.5, maxY: 7.5 }}
/>
<autoroutingphase
name="UART0_HEADER_GROUND_DROP"
phaseIndex={UART0_HEADER_GROUND_PHASE}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 46, maxX: 54, minY: 27.5, maxY: 30.5 }}
/>
<autoroutingphase
name="UART0_RX_ROUTE"
phaseIndex={UART0_ROUTE_PHASE.RX}
autorouter="default"
region={{ shape: "rect", minX: 20.5, maxX: 54, minY: 5, maxY: 31 }}
/>
<autoroutingphase
name="UART0_TX_ROUTE"
phaseIndex={UART0_ROUTE_PHASE.TX}
autorouter="default"
region={{ shape: "rect", minX: 20.5, maxX: 54, minY: 5, maxY: 31 }}
/>
<autoroutingphase
name="USB0_DATA_ESCAPE"
phaseIndex={USB0_ESCAPE_PHASE}
autorouter="default"
region={{ shape: "rect", minX: -3, maxX: 8, minY: -16, maxY: -9 }}
/>
<autoroutingphase
name="USB0_ANALOG_SOC_LINKS"
phaseIndex={USB0_ANALOG_PHASE.SOC_LINKS}
autorouter="default"
region={{ shape: "rect", minX: 0, maxX: 15.5, minY: -21, maxY: -9 }}
/>
<autoroutingphase
name="USB0_ESD_SOC_DATA_PHASE"
phaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_ESD}
autorouter="default"
region={{ shape: "rect", minX: 2.5, maxX: 4.5, minY: -18, maxY: -14 }}
/>
<autoroutingphase
name="USB0_ESD_CONNECTOR_DATA_PHASE"
phaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_CONNECTOR}
autorouter="default"
region={{ shape: "rect", minX: 7, maxX: 10, minY: -19, maxY: -15.5 }}
/>
<autoroutingphase
name="USB0_ESD_GROUND_DROP"
phaseIndex={USB0_CONNECTOR_PHASE.ESD_GROUND}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 5.5, maxX: 6.5, minY: -18.6, maxY: -17.6 }}
/>
<autoroutingphase
name="USB0_CONNECTOR_GROUND_DROP"
phaseIndex={USB0_CONNECTOR_PHASE.GND}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 2.5, maxX: 4.5, minY: -19, maxY: -17 }}
/>
<autoroutingphase
name="USB0_ANALOG_CONNECTOR_VBUS"
phaseIndex={USB0_ANALOG_PHASE.CONNECTOR_VBUS}
autorouter="default"
region={{ shape: "rect", minX: 10.5, maxX: 15, minY: -19, maxY: -17 }}
/>
<autoroutingphase
name="USB0_ANALOG_GROUND_DROP"
phaseIndex={USB0_ANALOG_PHASE.GROUND}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
region={{ shape: "rect", minX: 27.5, maxX: 29, minY: -21, maxY: -19 }}
/>
<autoroutingphase
name="POWER_INPUT_VSYS_FEED"
phaseIndex={POWER_INPUT_VSYS_ROUTE_PHASE}
autorouter="default"
region={{
shape: "rect",
minX: 14.99,
maxX: 23,
minY: -34.7,
maxY: 30,
}}
/>
<autoroutingphase
name="HDMI_CONNECTOR_GROUND_ROUTES_A"
phaseIndex={20.1}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="HDMI_CONNECTOR_GROUND_ROUTES_B"
phaseIndex={20.2}
autorouter="fanout"
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{ inner1: ["GND"] }}
/>
<autoroutingphase
name="HDMI_TMDS_SOURCE_CLOCK_PAIR"
phaseIndex={20.32}
autorouter="default"
/>
<autoroutingphase
name="HDMI_TMDS_SOURCE_DATA2_PAIR"
phaseIndex={20.33}
autorouter="default"
/>
<autoroutingphase
name="HDMI_TMDS_SOURCE_DATA1_PAIR"
phaseIndex={20.3}
autorouter="default"
/>
<autoroutingphase
name="HDMI_TMDS_SOURCE_DATA0_PAIR"
phaseIndex={20.31}
autorouter="default"
/>
<autoroutingphase
name="HDMI_TMDS_CONNECTOR_ROUTES"
phaseIndex={20.4}
autorouter="default"
/>
<autoroutingphase
name="HDMI_DVDD_SUPPLY_NET"
phaseIndex={20.5}
autorouter="default"
/>
<autoroutingphase
name="DDR_STRAP_ROUTES"
phaseIndex={27}
autorouter="default"
region={{ shape: "rect", minX: -21, maxX: -10, minY: -8, maxY: 8 }}
/>
<autoroutingphase
name="MCU_OSC0_ROUTES"
phaseIndex={16.9}
autorouter="default"
region={{ shape: "rect", minX: -12, maxX: -3.3, minY: 9, maxY: 22 }}
/>
<autoroutingphase
name="PMIC_CONTROL_ROUTES"
phaseIndex={29}
autorouter="default"
region={{ shape: "rect", minX: 4.5, maxX: 13, minY: 9, maxY: 13.5 }}
/>
<autoroutingphase
name="PMIC_RESET_SIGNAL_ROUTE"
phaseIndex={PMIC_RESET_ROUTE_PHASE.SIGNAL}
autorouter="default"
region={{ shape: "rect", minX: -4.5, maxX: 8, minY: 9, maxY: 14.5 }}
/>
<autoroutingphase
name="PMIC_RESET_PULLUP_SIGNAL_ROUTE"
phaseIndex={PMIC_RESET_ROUTE_PHASE.PULLUP_SIGNAL}
autorouter="default"
region={{ shape: "rect", minX: 4, maxX: 8, minY: 12, maxY: 22.5 }}
/>
<autoroutingphase
name="PMIC_RESET_PULLUP_SUPPLY_ROUTE"
phaseIndex={PMIC_RESET_ROUTE_PHASE.PULLUP_SUPPLY}
autorouter="default"
region={{ shape: "rect", minX: 4, maxX: 19, minY: 11, maxY: 17 }}
/>
<autoroutingphase
name="PMIC_LPM_SIGNAL_ROUTE"
phaseIndex={PMIC_LPM_ROUTE_PHASE.SIGNAL}
autorouter="default"
region={{ shape: "rect", minX: -2, maxX: 14.5, minY: 9.7, maxY: 18.5 }}
/>
<autoroutingphase
name="PMIC_LPM_PMIC_LINK_ROUTE"
phaseIndex={PMIC_LPM_ROUTE_PHASE.PMIC_LINK}
autorouter="default"
region={{ shape: "rect", minX: 9.5, maxX: 14.5, minY: 15.5, maxY: 18.5 }}
/>
<autoroutingphase
name="PMIC_LPM_PULLUP_SUPPLY_ROUTE"
phaseIndex={PMIC_LPM_ROUTE_PHASE.PULLUP_SUPPLY}
autorouter="default"
region={{ shape: "rect", minX: 9.5, maxX: 18.5, minY: 14.5, maxY: 18 }}
/>
<autoroutingphase
name="PMIC_INTERRUPT_SIGNAL_ROUTE"
phaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.SIGNAL}
autorouter="default"
region={{ shape: "rect", minX: -2, maxX: 14.5, minY: 8.8, maxY: 25 }}
/>
<autoroutingphase
name="PMIC_INTERRUPT_PMIC_LINK_ROUTE"
phaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.PMIC_LINK}
autorouter="default"
region={{ shape: "rect", minX: 9, maxX: 12.5, minY: 21.5, maxY: 25 }}
/>
<autoroutingphase
name="PMIC_INTERRUPT_PULLUP_SUPPLY_ROUTE"
phaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.PULLUP_SUPPLY}
autorouter="default"
region={{ shape: "rect", minX: 10.5, maxX: 14.5, minY: 23.5, maxY: 25.5 }}
/>
<autoroutingphase
name="VOUT_PCLK_ROUTE"
phaseIndex={VOUT_ROUTE_PHASE.PCLK}
autorouter="default"
region={{ shape: "rect", minX: -18, maxX: 13, minY: -14.5, maxY: -11.5 }}
/>
<autoroutingphase
name="VOUT_DE_ROUTE"
phaseIndex={VOUT_ROUTE_PHASE.DE}
autorouter="default"
region={{ shape: "rect", minX: -18, maxX: 13, minY: -14.5, maxY: -10 }}
/>
<autoroutingphase
name="VOUT_HSYNC_ROUTE"
phaseIndex={VOUT_ROUTE_PHASE.HSYNC}
autorouter="default"
region={{ shape: "rect", minX: -18, maxX: 13, minY: -21, maxY: 7.5 }}
/>
<autoroutingphase
name="VOUT_VSYNC_LOCAL_LINK"
phaseIndex={VOUT_ROUTE_PHASE.VSYNC_LOCAL}
autorouter="default"
region={{ shape: "rect", minX: -27, maxX: -16, minY: 4.5, maxY: 8.5 }}
/>
<autoroutingphase
name="VOUT_VSYNC_ROUTE"
phaseIndex={VOUT_ROUTE_PHASE.VSYNC}
autorouter="default"
region={{ shape: "rect", minX: -18, maxX: 13, minY: -21, maxY: 8.5 }}
/>
<breakout
name="SOC_FANOUT"
pcbX={0}
pcbY={0}
width="26mm"
height="30mm"
autorouter={{
preset: "fanout",
algorithmFn: createCachedSocFanoutAutorouter,
}}
fanoutRoutingLayers={[...SIGNAL_LAYERS]}
fanoutPourNetMap={{
inner1: ["GND"],
inner2: ["VDD_CORE_0V85"],
bottom: ["VDD_DDR_1V1"],
}}
busFanoutDirections={ACTIVE_BUS_DIRECTIONS}
>
<Am625Sip name="U1" noSchematicRepresentation />
{ACTIVE_BREAKOUT_BUSES.map(({ name, points }) => (
<Fragment key={name}>
{points.map(({ ball, pcbX, pcbY }) => (
<Fragment key={`${name}-${ball}`}>
<breakoutpoint
connection={`.U1 > .${ball}`}
pcbX={pcbX}
pcbY={pcbY}
/>
</Fragment>
))}
</Fragment>
))}
{SOC_GROUND_BALLS.map((ball) => (
<Fragment key={`SOC_GND_${ball}`}>
<trace from={`.U1 > .${ball}`} to="net.GND" width="0.2mm" />
</Fragment>
))}
{SOC_CORE_BALLS.map((ball) => (
<Fragment key={`SOC_CORE_${ball}`}>
<trace
from={`.U1 > .${ball}`}
to="net.VDD_CORE_0V85"
width="0.2mm"
/>
</Fragment>
))}
{SOC_DDR_1P1_BALLS.map((ball) => (
<Fragment key={`SOC_DDR_1P1_${ball}`}>
<trace
from={`.U1 > .${ball}`}
to="net.VDD_DDR_1V1"
width="0.2mm"
/>
</Fragment>
))}
{SOC_IO_1P8_BUSES.flatMap(({ points }) => points).map(({ ball }) => (
<Fragment key={`SOC_IO_1P8_${ball}`}>
<trace
name={`SOC_IO_1P8_${ball}`}
from={`.U1 > .${ball}`}
to="net.VDD_IO_1V8"
width="0.2mm"
/>
</Fragment>
))}
{SOC_ANALOG_1P8_BUSES.flatMap(({ points }) => points).map(({ ball }, index) => (
<Fragment key={`SOC_ANALOG_1P8_${ball}`}>
<trace
name={`SOC_ANALOG_1P8_${ball}`}
from={`.U1 > .${ball}`}
to="net.VDDA_1V8"
width="0.2mm"
routingPhaseIndex={getAnalogRoutePhase(index)}
/>
</Fragment>
))}
</breakout>
<net name="GND" routingPhaseIndex={1} />
{SOC_IO_1P8_FANOUT_BUSES.map(
({ name, balls, preferredLayers }) => (
<Fragment key={name}>
<bus
name={name}
connections={balls.map((ball) => `SOC_IO_1P8_${ball}`)}
preferredLayers={[...preferredLayers]}
/>
</Fragment>
),
)}
{SOC_ANALOG_1P8_PINNED_FANOUT_BUSES.map(
({ name, balls, preferredLayers }) => (
<Fragment key={name}>
<bus
name={name}
connections={balls.map((ball) => `SOC_ANALOG_1P8_${ball}`)}
preferredLayers={[...preferredLayers]}
/>
</Fragment>
),
)}
<copperpour
name="GND_PLANE"
layer="inner1"
connectsTo="net.GND"
clearance="0.15mm"
boardEdgeMargin="0.3mm"
/>
<copperpour
name="VDD_CORE_PLANE"
layer="inner2"
connectsTo="net.VDD_CORE_0V85"
clearance="0.15mm"
boardEdgeMargin="0.3mm"
/>
<copperpour
name="VDD_DDR_1P1_PLANE"
layer="bottom"
connectsTo="net.VDD_DDR_1V1"
clearance="0.15mm"
boardEdgeMargin="0.3mm"
/>
<capacitor
name="C24"
capacitance="10uF"
maxVoltageRating="6.3V"
footprint="0603"
supplierPartNumbers={{ jlcpcb: ["C19702"] }}
pcbX={-8.5}
pcbY={-5}
pcbRotation={270}
/>
<capacitor
name="C25"
capacitance="4.7uF"
maxVoltageRating="10V"
footprint="0402"
supplierPartNumbers={{ jlcpcb: ["C23733"] }}
pcbX={-8.5}
pcbY={-0.5}
pcbRotation={90}
/>
<capacitor
name="C26"
capacitance="1uF"
maxVoltageRating="10V"
footprint="0402"
supplierPartNumbers={{ jlcpcb: ["C52923"] }}
pcbX={-8.5}
pcbY={2}
pcbRotation={90}
/>
{["C24", "C25", "C26"].map((name) => (
<Fragment key={`${name}-soc-core-bulk`}>
<trace
from={`.${name} > .pin1`}
to="net.VDD_CORE_0V85"
width="0.2mm"
routingPhaseIndex={3}
/>
<trace
from={`.${name} > .pin2`}
to="net.GND"
width="0.2mm"
routingPhaseIndex={3}
/>
</Fragment>
))}
{[
{ name: "C27", x: -6 },
{ name: "C28", x: -4 },
{ name: "C29", x: -2 },
{ name: "C30", x: 2 },
{ name: "C31", x: 4 },
{ name: "C32", x: 7.5 },
].map(({ name, x }) => (
<Fragment key={`${name}-soc-core-hf`}>
<capacitor
name={name}
capacitance="100nF"
maxVoltageRating="10V"
footprint="0201"
supplierPartNumbers={{ jlcpcb: ["C1525"] }}
pcbX={x}
pcbY={-7}
/>
<trace
from={`.${name} > .pin1`}
to="net.VDD_CORE_0V85"
routingPhaseIndex={3}
/>
<trace
from={`.${name} > .pin2`}
to="net.GND"
routingPhaseIndex={3}
/>
</Fragment>
))}
<capacitor
name="C33"
capacitance="10uF"
maxVoltageRating="6.3V"
footprint="0603"
supplierPartNumbers={{ jlcpcb: ["C19702"] }}
pcbX={14.5}
pcbY={-3}
pcbRotation={90}
/>
<capacitor
name="C34"
capacitance="4.7uF"
maxVoltageRating="10V"
footprint="0402"
supplierPartNumbers={{ jlcpcb: ["C23733"] }}
pcbX={14.5}
pcbY={-5.8}
pcbRotation={90}
/>
<capacitor
name="C35"
capacitance="1uF"
maxVoltageRating="10V"
footprint="0402"
supplierPartNumbers={{ jlcpcb: ["C52923"] }}
pcbX={14.5}
pcbY={-10.5}
pcbRotation={90}
/>
{[
{ name: "C33", phase: 6 },
{ name: "C34", phase: 7 },
{ name: "C35", phase: 8 },
].map(({ name, phase }) => (
<Fragment key={`${name}-soc-ddr-bulk`}>
<trace
from={`.${name} > .pin1`}
to="net.VDD_DDR_1V1"
width="0.2mm"
routingPhaseIndex={phase}
/>
<trace
from={`.${name} > .pin2`}
to="net.GND"
width="0.2mm"
routingPhaseIndex={phase}
/>
</Fragment>
))}
{[
{ name: "C36", x: -7, phase: 5 },
{ name: "C37", x: -4, phase: 5 },
{ name: "C38", x: -2, phase: 5 },
{ name: "C39", x: 2, phase: 9 },
{ name: "C40", x: 4, phase: 9 },
{ name: "C41", x: 6, phase: 9 },
].map(({ name, x, phase }) => (
<Fragment key={`${name}-soc-ddr-hf`}>
<capacitor
name={name}
capacitance="100nF"
maxVoltageRating="10V"
footprint="0201"
supplierPartNumbers={{ jlcpcb: ["C1525"] }}
pcbX={x}
pcbY={-9}
/>
<trace
from={`.${name} > .pin1`}
to="net.VDD_DDR_1V1"
routingPhaseIndex={phase}
/>
<trace
from={`.${name} > .pin2`}
to="net.GND"
routingPhaseIndex={phase}
/>
</Fragment>
))}
<capacitor
name="C42"
capacitance="4.7uF"
maxVoltageRating="10V"
footprint="0402"
supplierPartNumbers={{ jlcpcb: ["C23733"] }}
pcbX={10}
pcbY={-17}
/>
<capacitor
name="C43"
capacitance="1uF"
maxVoltageRating="10V"
footprint="0402"
supplierPartNumbers={{ jlcpcb: ["C52923"] }}
pcbX={13}
pcbY={-17}
/>
{[
{ name: "C42", groundPhase: 12, supplyPhase: 17.22 },
{ name: "C43", groundPhase: 12.1, supplyPhase: 17.23 },
].map(({ name, groundPhase, supplyPhase }) => (
<Fragment key={`${name}-soc-analog-bulk`}>
<trace
from={`.${name} > .pin1`}
to="net.VDDA_1V8"
width="0.2mm"
routingPhaseIndex={supplyPhase}
/>
<trace
from={`.${name} > .pin2`}
to="net.GND"
routingPhaseIndex={groundPhase}
/>
</Fragment>
))}
{CAP_VDDS_BREAKOUT_BUSES.map(({ name, points, preferredLayers }) => (
<Fragment key={`${name}-fanout-bus`}>
<bus
name={name}
connections={points.map(({ ball }) => `CAP_VDDS_${ball}`)}
preferredLayers={preferredLayers}
/>
</Fragment>
))}
<subcircuit
name="CAP_VDDS_CACHE"
circuitJson={capVddsCircuitJson}
pcbX={0}
pcbY={0}
exposedNets={["GND"]}
/>
{CAP_VDDS_LINKS.map(({ ball }, index) => (
<Fragment key={`CAP_VDDS_${ball}`}>
<trace
name={`CAP_VDDS_${ball}`}
from={`.U1 > .${ball}`}
to={`.CAP_VDDS_CACHE .CAP_VDDS .X_${ball} > .pin1`}
routingPhaseIndex={getAnalogRoutePhase(10 + index)}
maxLength={ball === "U7" || ball === "W17" ? "14mm" : "12mm"}
/>
</Fragment>
))}
<resistor
name="R7"
resistance="10k"
footprint="0201"
supplierPartNumbers={{ jlcpcb: ["C473048"] }}
pcbX={-19}
pcbY={6}
/>
<resistor
name="R8"
resistance="240"
footprint="0201"
pcbX={-19}
pcbY={-3}
pcbRotation={90}
/>
<resistor
name="R9"
resistance="240"
footprint="0201"
pcbX={-18}
pcbY={-6}
/>
<bus
name="DDR_STRAPS"
connections={["DDR0_RESET0_N", "DDR0_CAL0", "DDR_ZQ"]}
preferredLayers={DDR_STRAPS_BUS.preferredLayers}
routingPhaseIndex={27}
/>
<trace
name="DDR0_RESET0_N"
from=".U1 > .G1"
to=".R7 > .pin1"
routingPhaseIndex={27}
/>
<trace
name="DDR0_CAL0"
from=".U1 > .M2"
to=".R8 > .pin1"
routingPhaseIndex={27}
/>
<trace
name="DDR_ZQ"
from=".U1 > .R3"
to=".R9 > .pin1"
routingPhaseIndex={27}
/>
<trace from=".R7 > .pin2" to="net.GND" routingPhaseIndex={10} />
<trace from=".R8 > .pin2" to="net.GND" routingPhaseIndex={10} />
<trace
from=".R9 > .pin2"
to="net.VDD_DDR_1V1"
routingPhaseIndex={11}
/>
<X322525MOB4SI name="Y1" pcbX={-8} pcbY={20} />
<capacitor
name="C1"
capacitance="22pF"
maxVoltageRating="25V"
footprint="0201"
pcbX={-11.3}
pcbY={19.15}
pcbRotation={180}
/>
<capacitor
name="C2"
capacitance="22pF"
maxVoltageRating="25V"
footprint="0201"
pcbX={-4.9}
pcbY={20.85}
/>
<bus
name="MCU_OSC0"
connections={["MCU_OSC0_B2", "MCU_OSC0_A3"]}
preferredLayers={MCU_OSC0_BUS.preferredLayers}
routingPhaseIndex={16.9}
/>
<trace
name="MCU_OSC0_B2"
from=".U1 > .B2"
to=".Y1 > .OSC1"
routingPhaseIndex={16.9}
/>
<trace
name="MCU_OSC0_A3"
from=".U1 > .A3"
to=".Y1 > .OSC2"
routingPhaseIndex={16.9}
/>
<trace
from=".Y1 > .OSC1"
to=".C1 > .pin1"
routingPhaseIndex={16.9}
/>
<trace
from=".Y1 > .OSC2"
to=".C2 > .pin1"
routingPhaseIndex={16.9}
/>
<trace from=".Y1 > .GND1" to="net.GND" routingPhaseIndex={0} />
<trace from=".Y1 > .GND2" to="net.GND" routingPhaseIndex={0} />
<trace from=".C1 > .pin2" to="net.GND" routingPhaseIndex={0} />
<trace from=".C2 > .pin2" to="net.GND" routingPhaseIndex={0} />
<bus
name="MMC1_MICROSD"
connections={MMC1_BOOT_CONNECTIONS.map(
({ ball }) => `MMC1_ESCAPE_${ball}`,
)}
preferredLayers={MMC1_BOOT_BUS.preferredLayers}
routingPhaseIndex={21}
/>
{MMC1_BOOT_CONNECTIONS.map(({ ball, pin }) => (
<trace
key={`MMC1_MICROSD-${ball}`}
name={`MMC1_ESCAPE_${ball}`}
from={`.U1 > .${ball}`}
to={`.MICROSD .X_SOC_${pin} > .pin1`}
routingPhaseIndex={21}
/>
))}
<subcircuit
name="MICROSD"
circuitJson={microSdCircuitJson}
pcbX={30.2}
pcbY={0}
schTraceAutoLabelEnabled
/>
<trace
name="MICROSD_VDD_LINK"
from=".MICROSD .X_VDD > .pin1"
to=".C8 > .pin1"
width="0.2mm"
routingPhaseIndex={25}
/>
<trace
name="MICROSD_GND_LINK"
from=".MICROSD .X_GND > .pin1"
to="net.GND"
width="0.3mm"
routingPhaseIndex={25.1}
/>
<bus
name="PMIC_CONTROL"
connections={["PMIC_SDA", "PMIC_SCL"]}
preferredLayers={PMIC_RUNTIME_BUS.preferredLayers}
routingPhaseIndex={29}
/>
<bus
name="PMIC_RESET_SOC_BUS"
connections={["PMIC_RESET_SOC_LINK"]}
preferredLayers={["inner2"]}
routingPhaseIndex={PMIC_RESET_ROUTE_PHASE.SIGNAL}
/>
<trace
name="PMIC_RESET_SOC_LINK"
from=".U1 > .D2"
to=".R16 > .pin1"
routingPhaseIndex={PMIC_RESET_ROUTE_PHASE.SIGNAL}
/>
<trace
name="PMIC_SDA"
from=".R11 > .pin2"
to=".U1 > .A16"
routingPhaseIndex={29}
/>
<trace
name="PMIC_SCL"
from=".R12 > .pin2"
to=".U1 > .B16"
routingPhaseIndex={29}
/>
<net name="VDD_CORE_0V85" routingPhaseIndex={3} />
<net name="VDD_IO_1V8" routingPhaseIndex={23} />
<net name="VDD_DDR_1V1" routingPhaseIndex={4} />
<net name="VDDA_1V8" routingPhaseIndex={17.3} />
<bus
name="VOUT_CONTROL_FAST"
connections={ACTIVE_VOUT_CONTROL_CONNECTIONS.slice(0, 2).map(
({ name }) => name,
)}
preferredLayers={VOUT_CONTROL_FAST_BUS.preferredLayers}
/>
<bus
name="VOUT_HSYNC_ESCAPE"
connections={ACTIVE_VOUT_CONTROL_CONNECTIONS.slice(2).map(
({ name }) => name,
)}
preferredLayers={VOUT_HSYNC_ESCAPE_BUS.preferredLayers}
/>
{ACTIVE_VOUT_CONTROL_CONNECTIONS.map(({ name, ball, routingPhase }) => (
<trace
key={name}
name={name}
from={`.U1 > .${ball}`}
to={
name === "VOUT0_VSYNC"
? ".HDMI_VSYNC_BOUNDARY > .pin1"
: `.HDMI_CACHE .HDMI .X_${name} > .pin1`
}
routingPhaseIndex={routingPhase}
/>
))}
<subcircuit
name="HDMI_CACHE"
circuitJson={hdmiCircuitJson}
pcbX={0}
pcbY={0}
/>
<subcircuit
name="PMIC_CACHE"
circuitJson={pmicVsysCircuitJson}
pcbX={0}
pcbY={0}
/>
<resistor
name="R16"
resistance="10k"
footprint="0201"
supplierPartNumbers={{ jlcpcb: ["C473048"] }}
pcbX={5.5}
pcbY={13}
/>
<bus
name="PMIC_RESET_PMIC_BUS"
connections={["PMIC_RESET_PMIC_LINK"]}
preferredLayers={["bottom"]}
routingPhaseIndex={PMIC_RESET_ROUTE_PHASE.PULLUP_SIGNAL}
/>
<trace
name="PMIC_RESET_PMIC_LINK"
from=".R16 > .pin1"
to=".U2 > .nRSTOUT"
routingPhaseIndex={PMIC_RESET_ROUTE_PHASE.PULLUP_SIGNAL}
/>
<bus
name="PMIC_RESET_PULLUP_SUPPLY_BUS"
connections={["PMIC_RESET_PULLUP_SUPPLY"]}
preferredLayers={["bottom"]}
routingPhaseIndex={PMIC_RESET_ROUTE_PHASE.PULLUP_SUPPLY}
/>
<trace
name="PMIC_RESET_PULLUP_SUPPLY"
from=".R16 > .pin2"
to=".C13 > .pin1"
routingPhaseIndex={PMIC_RESET_ROUTE_PHASE.PULLUP_SUPPLY}
/>
<resistor
name="R17"
resistance="10k"
footprint="0201"
supplierPartNumbers={{ jlcpcb: ["C473048"] }}
pcbX={13.8}
pcbY={16.35}
/>
<bus
name="PMIC_LPM_SOC_BUS"
connections={["PMIC_LPM_SOC_LINK"]}
preferredLayers={["inner2"]}
routingPhaseIndex={PMIC_LPM_ROUTE_PHASE.SIGNAL}
/>
<trace
name="PMIC_LPM_SOC_LINK"
from=".U1 > .B7"
to=".R17 > .pin1"
routingPhaseIndex={PMIC_LPM_ROUTE_PHASE.SIGNAL}
/>
<bus
name="PMIC_LPM_PMIC_BUS"
connections={["PMIC_LPM_PMIC_LINK"]}
preferredLayers={["top"]}
routingPhaseIndex={PMIC_LPM_ROUTE_PHASE.PMIC_LINK}
/>
<trace
name="PMIC_LPM_PMIC_LINK"
from=".R17 > .pin1"
to=".U2 > .MODE_STBY"
routingPhaseIndex={PMIC_LPM_ROUTE_PHASE.PMIC_LINK}
/>
<bus
name="PMIC_LPM_PULLUP_SUPPLY_BUS"
connections={["PMIC_LPM_PULLUP_SUPPLY"]}
preferredLayers={["top"]}
routingPhaseIndex={PMIC_LPM_ROUTE_PHASE.PULLUP_SUPPLY}
/>
<trace
name="PMIC_LPM_PULLUP_SUPPLY"
from=".R17 > .pin2"
to=".C13 > .pin1"
routingPhaseIndex={PMIC_LPM_ROUTE_PHASE.PULLUP_SUPPLY}
/>
<resistor
name="R18"
resistance="10k"
footprint="0201"
supplierPartNumbers={{ jlcpcb: ["C473048"] }}
pcbX={11.5}
pcbY={24.5}
/>
<bus
name="PMIC_INTERRUPT_SOC_BUS"
connections={["PMIC_INTERRUPT_SOC_LINK"]}
preferredLayers={["inner2"]}
routingPhaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.SIGNAL}
/>
<trace
name="PMIC_INTERRUPT_SOC_LINK"
from=".U1 > .D16"
to=".U2 > .nINT"
routingPhaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.SIGNAL}
/>
<bus
name="PMIC_INTERRUPT_PMIC_BUS"
connections={["PMIC_INTERRUPT_PMIC_LINK"]}
preferredLayers={["top"]}
routingPhaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.PMIC_LINK}
/>
<trace
name="PMIC_INTERRUPT_PMIC_LINK"
from=".R18 > .pin1"
to=".U2 > .nINT"
routingPhaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.PMIC_LINK}
/>
<bus
name="PMIC_INTERRUPT_PULLUP_SUPPLY_BUS"
connections={["PMIC_INTERRUPT_PULLUP_SUPPLY"]}
preferredLayers={["top"]}
routingPhaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.PULLUP_SUPPLY}
/>
<trace
name="PMIC_INTERRUPT_PULLUP_SUPPLY"
from=".R18 > .pin2"
to=".R3 > .pin2"
routingPhaseIndex={PMIC_INTERRUPT_ROUTE_PHASE.PULLUP_SUPPLY}
/>
<resistor
name="R15"
resistance="0"
footprint="0201"
pcbX={5.3}
pcbY={16.9}
pcbRotation={90}
/>
<trace
name="PMIC_BUCK2_INPUT_CAP"
from=".U2 > .PVIN_B2"
to=".C4 > .pin1"
width="0.3mm"
routingPhaseIndex={getPmicInputRoutePhase(2)}
/>
<trace
name="PMIC_BUCK2_INPUT_LINK"
from=".C4 > .pin1"
to=".R13 > .pin1"
width="0.3mm"
routingPhaseIndex={getPmicInputRoutePhase(2)}
/>
<trace
from=".U2 > .PVIN_B3"
to=".C5 > .pin1"
width="0.3mm"
routingPhaseIndex={getPmicInputRoutePhase(4)}
/>
<trace
from=".U2 > .VDD1P8"
to=".C7 > .pin1"
routingPhaseIndex={getPmicInputRoutePhase(8)}
/>
<trace
name="PMIC_AGND_DROP"
from=".U2 > .AGND"
to="net.GND"
routingPhaseIndex={1}
/>
<trace
from=".U2 > .GND"
to=".U2 > .AGND"
width="0.5mm"
routingPhaseIndex={1.005}
/>
{[
{ name: "C3", phase: 1.01 },
{ name: "C4", phase: 1.011 },
{ name: "C5", phase: 1.012 },
].map(({ name, phase }) => (
<trace key={`${name}-gnd`} from={`.${name} > .pin2`} to="net.GND" routingPhaseIndex={phase} />
))}
<trace
from=".C6 > .pin2"
to="net.GND"
routingPhaseIndex={1.02}
/>
<trace
from=".C7 > .pin2"
to="net.GND"
routingPhaseIndex={1.02}
/>
<bus
name="PMIC_VDD_SD_LOCAL_BUS"
connections={["PMIC_VDD_SD_LOCAL"]}
routingPhaseIndex={21.4}
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<trace
name="PMIC_VDD_SD_LOCAL"
from=".U2 > .VLDO1"
to=".C8 > .pin1"
width="0.2mm"
routingPhaseIndex={21.4}
/>
<trace from=".C8 > .pin2" to="net.GND" routingPhaseIndex={1.1} />
<trace
from=".U2 > .PVIN_LDO2"
to=".C9 > .pin1"
width="0.2mm"
routingPhaseIndex={PMIC_LDO2_ROUTE_PHASES.LOCAL}
/>
<trace
name="PMIC_LDO2_ISOLATION"
from=".C9 > .pin1"
to=".R15 > .pin1"
width="0.2mm"
routingPhaseIndex={PMIC_LDO2_ROUTE_PHASES.ISOLATION}
/>
<trace
name="PMIC_LDO2_FEED"
from=".R15 > .pin2"
to=".C13 > .pin1"
width="0.2mm"
routingPhaseIndex={PMIC_LDO2_ROUTE_PHASES.FEED}
/>
<trace
from=".C9 > .pin2"
to="net.GND"
routingPhaseIndex={1.1}
/>
<trace
from=".U2 > .PVIN_LDO34"
to=".C19 > .pin1"
width="0.3mm"
routingPhaseIndex={24.03}
/>
<trace
from=".C19 > .pin1"
to=".R14 > .pin1"
width="0.3mm"
routingPhaseIndex={24.04}
/>
<trace
from=".C19 > .pin2"
to="net.GND"
routingPhaseIndex={1.1}
/>
<trace
name="PMIC_VDDA_1V8_SOURCE"
from=".U2 > .VLDO3"
to=".C20 > .pin1"
width="0.2mm"
routingPhaseIndex={17.2}
/>
<trace
from=".C20 > .pin1"
to="net.VDDA_1V8"
width="0.2mm"
routingPhaseIndex={17.21}
/>
<trace
from=".C20 > .pin2"
to="net.GND"
routingPhaseIndex={1.1}
/>
<trace
from=".U2 > .VLDO4"
to=".C21 > .pin1"
width="0.2mm"
routingPhaseIndex={24.05}
/>
<trace
from=".C21 > .pin2"
to="net.GND"
routingPhaseIndex={1.1}
/>
<bus
name="PMIC_ENABLE_LOCAL_BUS"
connections={["PMIC_ENABLE_LOCAL"]}
routingPhaseIndex={24.1}
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<trace
name="PMIC_ENABLE_LOCAL"
from=".U2 > .EN_PB_VSENSE"
to=".R1 > .pin1"
routingPhaseIndex={24.1}
/>
<bus
name="PMIC_VSEL_LOCAL_BUS"
connections={["PMIC_VSEL_LOCAL"]}
routingPhaseIndex={24.11}
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<trace
name="PMIC_VSEL_LOCAL"
from=".U2 > .VSEL_SD_VSEL_DDR"
to=".R2 > .pin1"
routingPhaseIndex={24.11}
/>
<bus
name="PMIC_SDA_LOCAL_BUS"
connections={["PMIC_SDA_PULLUP", "PMIC_SDA_HANDOFF"]}
routingPhaseIndex={22.2}
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<bus
name="PMIC_SCL_LOCAL_BUS"
connections={["PMIC_SCL_PULLUP", "PMIC_SCL_HANDOFF"]}
routingPhaseIndex={22.3}
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<trace
name="PMIC_SDA_PULLUP"
from=".R3 > .pin1"
to=".U2 > .SDA"
routingPhaseIndex={22.2}
/>
<trace
from=".R3 > .pin2"
to=".C13 > .pin1"
routingPhaseIndex={24.4}
/>
<trace
name="PMIC_SCL_PULLUP"
from=".R4 > .pin1"
to=".U2 > .SCL"
routingPhaseIndex={22.3}
/>
<trace
from=".R4 > .pin2"
to=".C13 > .pin1"
routingPhaseIndex={24.4}
/>
<trace
name="PMIC_SDA_HANDOFF"
from=".U2 > .SDA"
to=".R11 > .pin1"
routingPhaseIndex={22.2}
/>
<trace
name="PMIC_SCL_HANDOFF"
from=".U2 > .SCL"
to=".R12 > .pin1"
routingPhaseIndex={22.3}
/>
<trace
from=".U2 > .LX_B1_1"
to=".L1 > .pin1"
width="0.3mm"
routingPhaseIndex={22}
/>
<trace
from=".U2 > .LX_B1_2"
to=".L1 > .pin1"
width="0.3mm"
routingPhaseIndex={22}
/>
<trace
from=".L1 > .pin2"
to=".C10 > .pin1"
width="0.3mm"
routingPhaseIndex={22}
/>
<trace
from=".U2 > .FB_B1"
to=".C10 > .pin1"
routingPhaseIndex={22}
/>
<trace
from=".C11 > .pin1"
to=".C10 > .pin1"
width="0.3mm"
routingPhaseIndex={22}
/>
<trace
from=".C12 > .pin1"
to=".C10 > .pin1"
width="0.3mm"
routingPhaseIndex={22}
/>
<trace
from=".C10 > .pin1"
to="net.VDD_CORE_0V85"
width="0.3mm"
routingPhaseIndex={3}
/>
{["C10", "C11", "C12"].map((name) => (
<trace
key={`${name}-buck1-gnd`}
from={`.${name} > .pin2`}
to="net.GND"
routingPhaseIndex={1.2}
/>
))}
<trace
from=".U2 > .LX_B2"
to=".L2 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".L2 > .pin2"
to=".C13 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".U2 > .FB_B2"
to=".C13 > .pin1"
routingPhaseIndex={22.05}
/>
<trace
from=".C14 > .pin1"
to=".C13 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".C15 > .pin1"
to=".C13 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".C13 > .pin1"
to=".R10 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".R10 > .pin2"
to="net.VDD_IO_1V8"
width="0.3mm"
routingPhaseIndex={23}
/>
{["C13", "C14", "C15"].map((name) => (
<trace
key={`${name}-buck2-gnd`}
from={`.${name} > .pin2`}
to="net.GND"
routingPhaseIndex={1.3}
/>
))}
<trace
from=".U2 > .LX_B3"
to=".L3 > .pin2"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".L3 > .pin1"
to=".C16 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".U2 > .FB_B3"
to=".C16 > .pin1"
routingPhaseIndex={22.05}
/>
<trace
from=".C17 > .pin1"
to=".C16 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".C18 > .pin1"
to=".C16 > .pin1"
width="0.3mm"
routingPhaseIndex={22.05}
/>
<trace
from=".C16 > .pin1"
to="net.VDD_DDR_1V1"
width="0.3mm"
routingPhaseIndex={4}
/>
<trace
from=".C17 > .pin2"
to="net.GND"
width="0.3mm"
routingPhaseIndex={1.4}
/>
<trace
from=".C18 > .pin2"
to="net.GND"
width="0.3mm"
routingPhaseIndex={1.4}
/>
<trace
from=".C16 > .pin2"
to="net.GND"
width="0.3mm"
routingPhaseIndex={1.4}
/>
<trace
name="HDMI_3V3_FEED_FROM_VSYS"
from=".C3 > .pin1"
to=".HDMI_CACHE .HDMI .X_3V3 > .pin1"
width="0.3mm"
routingPhaseIndex={24.5}
/>
<PowerInputSubcircuit />
<trace
name="POWER_INPUT_GND_LINK"
from=".POWER_INPUT .X_GND > .pin1"
to="net.GND"
width="0.8mm"
routingPhaseIndex={26.1}
/>
<trace
name="POWER_INPUT_VSYS_LINK"
from=".POWER_INPUT .R23 > .pin2"
to=".C3 > .pin1"
width="0.5mm"
routingPhaseIndex={POWER_INPUT_VSYS_ROUTE_PHASE}
/>
<chip
name="HDMI_VSYNC_BOUNDARY"
pcbX={-17}
pcbY={7.5}
noSchematicRepresentation
footprint={
<footprint>
<smtpad
portHints={["pin1"]}
shape="rect"
width="0.8mm"
height="0.8mm"
/>
</footprint>
}
/>
<trace
name="HDMI_VSYNC_LOCAL_LINK"
from=".HDMI_VSYNC_BOUNDARY > .pin1"
to=".HDMI_CACHE .HDMI .U3 > .VSYNC"
routingPhaseIndex={VOUT_ROUTE_PHASE.VSYNC_LOCAL}
/>
{[
{ name: "UART0_RX_BOUNDARY", pcbX: 21, pcbY: 6.17872 },
{ name: "UART0_TX_BOUNDARY", pcbX: 22, pcbY: 5.85744 },
].map(({ name, pcbX, pcbY }) => (
<chip
key={name}
name={name}
pcbX={pcbX}
pcbY={pcbY}
noSchematicRepresentation
footprint={
<footprint>
<platedhole
portHints={["pin1"]}
shape="circle"
holeDiameter="0.3mm"
outerDiameter="0.7mm"
/>
</footprint>
}
/>
))}
<bus
name="UART0_ESCAPE"
connections={["UART0_RX_ESCAPE", "UART0_TX_ESCAPE"]}
preferredLayers={UART0_CONSOLE_BUS.preferredLayers}
/>
<trace
name="UART0_RX_ESCAPE"
from=".U1 > .D14"
to=".UART0_RX_BOUNDARY > .pin1"
routingPhaseIndex={UART0_ESCAPE_PHASE.RX}
/>
<trace
name="UART0_TX_ESCAPE"
from=".U1 > .E14"
to=".UART0_TX_BOUNDARY > .pin1"
routingPhaseIndex={UART0_ESCAPE_PHASE.TX}
/>
<chip
name="J4"
manufacturerPartNumber="UART0_1V8_DEBUG_HEADER"
pinLabels={{
pin1: ["GND"],
pin2: ["RX"],
pin3: ["TX"],
}}
pcbX={50}
pcbY={29}
noSchematicRepresentation
footprint={
<footprint>
<platedhole
portHints={["pin1"]}
pcbX={-2.54}
pcbY={0}
shape="circle"
holeDiameter="1mm"
outerDiameter="1.7mm"
/>
<platedhole
portHints={["pin2"]}
pcbX={0}
pcbY={0}
shape="circle"
holeDiameter="1mm"
outerDiameter="1.7mm"
/>
<platedhole
portHints={["pin3"]}
pcbX={2.54}
pcbY={0}
shape="circle"
holeDiameter="1mm"
outerDiameter="1.7mm"
/>
<silkscreenpath
route={[
{ x: -3.8, y: -1.3 },
{ x: 3.8, y: -1.3 },
{ x: 3.8, y: 1.3 },
{ x: -3.8, y: 1.3 },
{ x: -3.8, y: -1.3 },
]}
/>
<silkscreencircle pcbX={-2.54} pcbY={0} radius="1.05mm" />
</footprint>
}
/>
<bus
name="UART0_CONSOLE"
connections={["UART0_RX", "UART0_TX"]}
preferredLayers={UART0_CONSOLE_BUS.preferredLayers}
/>
<trace
name="UART0_HEADER_GND"
from=".J4 > .pin1"
to="net.GND"
width="0.3mm"
routingPhaseIndex={UART0_HEADER_GROUND_PHASE}
/>
<trace
name="UART0_RX"
from=".UART0_RX_BOUNDARY > .pin1"
to=".J4 > .pin2"
routingPhaseIndex={UART0_ROUTE_PHASE.RX}
/>
<trace
name="UART0_TX"
from=".UART0_TX_BOUNDARY > .pin1"
to=".J4 > .pin3"
routingPhaseIndex={UART0_ROUTE_PHASE.TX}
/>
{[
{ name: "USB0_DP_BOUNDARY", pcbX: 4, pcbY: -15 },
{ name: "USB0_DM_BOUNDARY", pcbX: 3.5, pcbY: -15 },
].map(({ name, pcbX, pcbY }) => (
<chip
key={name}
name={name}
pcbX={pcbX}
pcbY={pcbY}
noSchematicRepresentation
footprint={
<footprint>
<smtpad
portHints={["pin1"]}
shape="rect"
width="0.3mm"
height="0.3mm"
/>
</footprint>
}
/>
))}
<bus
name="USB0_DATA"
connections={["USB0_DP_ESCAPE", "USB0_DM_ESCAPE"]}
preferredLayers={USB0_DATA_BUS.preferredLayers}
/>
<trace
name="USB0_DP_ESCAPE"
from=".U1 > .AD11"
to=".USB0_DP_BOUNDARY > .pin1"
routingPhaseIndex={USB0_ESCAPE_PHASE}
/>
<trace
name="USB0_DM_ESCAPE"
from=".U1 > .AE11"
to=".USB0_DM_BOUNDARY > .pin1"
routingPhaseIndex={USB0_ESCAPE_PHASE}
/>
<subcircuit
name="USB_C_CACHE"
circuitJson={usbCDeviceCircuitJson}
pcbX={8}
pcbY={-26.2}
pcbRotation={-90}
/>
<subcircuit
name="USB0_ESD_CACHE"
circuitJson={usb0DataEsdCircuitJson}
pcbX={6}
pcbY={-16.6}
/>
<bus
name="USB0_ESD_SOC_DATA"
connections={["USB0_DP_TO_ESD", "USB0_DM_TO_ESD"]}
routingPhaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_ESD}
maxLengthSkew="0.2mm"
targetImpedance="45ohm"
pcbTraceWidth="0.15mm"
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<trace
name="USB0_DP_TO_ESD"
from=".USB0_DP_BOUNDARY > .pin1"
to=".USB0_ESD_CACHE .USB0_DATA_ESD .X_SOC_DP > .pin1"
width="0.15mm"
routingPhaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_ESD}
/>
<trace
name="USB0_DM_TO_ESD"
from=".USB0_DM_BOUNDARY > .pin1"
to=".USB0_ESD_CACHE .USB0_DATA_ESD .X_SOC_DM > .pin1"
width="0.15mm"
routingPhaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_ESD}
/>
<bus
name="USB0_ESD_CONNECTOR_DATA"
connections={["USB0_DP_FROM_ESD", "USB0_DM_FROM_ESD"]}
routingPhaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_CONNECTOR}
maxLengthSkew="0.2mm"
targetImpedance="45ohm"
pcbTraceWidth="0.15mm"
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<trace
name="USB0_DP_FROM_ESD"
from=".USB0_ESD_CACHE .USB0_DATA_ESD .X_CONNECTOR_DP > .pin1"
to=".USB_C_CACHE .USB_C_DEVICE .X_DP > .pin1"
width="0.15mm"
routingPhaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_CONNECTOR}
/>
<trace
name="USB0_DM_FROM_ESD"
from=".USB0_ESD_CACHE .USB0_DATA_ESD .X_CONNECTOR_DM > .pin1"
to=".USB_C_CACHE .USB_C_DEVICE .X_DM > .pin1"
width="0.15mm"
routingPhaseIndex={USB0_CONNECTOR_PHASE.DATA_TO_CONNECTOR}
/>
<trace
name="USB0_ESD_GND"
from=".USB0_ESD_CACHE .USB0_DATA_ESD .X_GND > .pin1"
to="net.GND"
width="0.3mm"
routingPhaseIndex={USB0_CONNECTOR_PHASE.ESD_GROUND}
/>
<trace
name="USB0_CONNECTOR_GND"
from=".USB_C_CACHE .USB_C_DEVICE .X_GND > .pin1"
to="net.GND"
width="0.3mm"
routingPhaseIndex={USB0_CONNECTOR_PHASE.GND}
/>
<subcircuit
name="USB0_ANALOG_CACHE"
circuitJson={usb0AnalogSupportCircuitJson}
pcbX={21.2}
pcbY={-18}
/>
<bus
name="USB0_ANALOG"
connections={["USB0_VBUS_SUPPORT", "USB0_RCALIB_SUPPORT"]}
routingPhaseIndex={USB0_ANALOG_PHASE.SOC_LINKS}
preferredLayers={USB0_ANALOG_BUS.preferredLayers}
/>
<trace
name="USB0_VBUS_SUPPORT"
from=".U1 > .AC11"
to=".USB0_ANALOG_CACHE .USB0_ANALOG_SUPPORT .X_SOC_VBUS > .pin1"
width="0.15mm"
routingPhaseIndex={USB0_ANALOG_PHASE.SOC_LINKS}
/>
<trace
name="USB0_RCALIB_SUPPORT"
from=".U1 > .AE10"
to=".USB0_ANALOG_CACHE .USB0_ANALOG_SUPPORT .X_RCALIB > .pin1"
width="0.15mm"
routingPhaseIndex={USB0_ANALOG_PHASE.SOC_LINKS}
/>
<trace
name="USB0_VBUS_FROM_CONNECTOR"
from=".USB_C_CACHE .USB_C_DEVICE .X_VBUS > .pin1"
to=".USB0_ANALOG_CACHE .USB0_ANALOG_SUPPORT .X_CONNECTOR_VBUS > .pin1"
width="0.3mm"
routingPhaseIndex={USB0_ANALOG_PHASE.CONNECTOR_VBUS}
/>
<trace
name="USB0_ANALOG_GND"
from=".USB0_ANALOG_CACHE .USB0_ANALOG_SUPPORT .X_GND > .pin1"
to="net.GND"
width="0.3mm"
routingPhaseIndex={USB0_ANALOG_PHASE.GROUND}
/>
<silkscreentext
text="USB0 VBUS SENSE"
pcbX={21.5}
pcbY={-22.2}
fontSize="0.6mm"
anchorAlignment="center"
/>
<silkscreentext
text="USB-C DEVICE"
pcbX={14}
pcbY={-29}
fontSize="0.7mm"
anchorAlignment="center"
/>
<silkscreentext
text="UART0 1V8"
pcbX={50}
pcbY={31.3}
fontSize="0.8mm"
anchorAlignment="center"
/>
<silkscreentext
text="G RX TX"
pcbX={50}
pcbY={26.9}
fontSize="0.65mm"
anchorAlignment="center"
/>
<pcbnotetext
pcbX={-12}
pcbY={-22.5}
fontSize="0.7mm"
text="AM625SIP Linux board — exact SiP + mandatory 25 MHz clock + boot fanout"
/>
<pcbnotetext
pcbX={-12}
pcbY={-23.7}
fontSize="0.55mm"
text="Incremental autorouting; TI 8/18 mil PTH escape is the final target"
/>
</board>
)
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