ShiboSoftwareDev/am625sip-linux-board
This code defines the physical footprint and pin layout for an AM625 System-in-Package (SIP) component, detailing pad positions, pin labels, and package outline for hardware integration.
- Version
- 1.0.24
- License
- unset
- Stars
- 0
subcircuits/cache/cap-vdds.circuit.json
PCB
Schematic
[
{
"type": "source_group",
"source_group_id": "source_group_0",
"name": "CAP_VDDS",
"is_subcircuit": true,
"was_automatically_named": false,
"subcircuit_id": "subcircuit_source_group_0",
"parent_source_group_id": "source_group_1",
"parent_subcircuit_id": "subcircuit_source_group_1"
},
{
"type": "source_group",
"source_group_id": "source_group_1",
"is_subcircuit": true,
"was_automatically_named": true,
"subcircuit_id": "subcircuit_source_group_1"
},
{
"type": "source_net",
"source_net_id": "source_net_0",
"name": "GND",
"member_source_group_ids": [],
"is_ground": true,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_1_connectivity_net0"
},
{
"type": "source_net",
"source_net_id": "source_net_1",
"name": "GND",
"member_source_group_ids": [],
"is_ground": true,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_1_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_0",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_0",
"ftype": "simple_chip",
"name": "X_G9",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_1",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_2",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_1",
"ftype": "simple_capacitor",
"name": "C44",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_3",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net2"
},
{
"type": "source_component",
"source_component_id": "source_component_2",
"ftype": "simple_chip",
"name": "X_H11",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_4",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_5",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_3",
"ftype": "simple_capacitor",
"name": "C45",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_6",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_4",
"ftype": "simple_chip",
"name": "X_H15",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_7",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_5",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_8",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_5",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_5",
"ftype": "simple_capacitor",
"name": "C46",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_9",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net4"
},
{
"type": "source_component",
"source_component_id": "source_component_6",
"ftype": "simple_chip",
"name": "X_H17",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_10",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_7",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_11",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_7",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_7",
"ftype": "simple_capacitor",
"name": "C47",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_12",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_8",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net5"
},
{
"type": "source_component",
"source_component_id": "source_component_8",
"ftype": "simple_chip",
"name": "X_J19",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_13",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_9",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net5"
},
{
"type": "source_port",
"source_port_id": "source_port_14",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_9",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_9",
"ftype": "simple_capacitor",
"name": "C48",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_15",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_10",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net6"
},
{
"type": "source_component",
"source_component_id": "source_component_10",
"ftype": "simple_chip",
"name": "X_K18",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_16",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_11",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net6"
},
{
"type": "source_port",
"source_port_id": "source_port_17",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_11",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_11",
"ftype": "simple_capacitor",
"name": "C49",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_18",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_12",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net7"
},
{
"type": "source_component",
"source_component_id": "source_component_12",
"ftype": "simple_chip",
"name": "X_P19",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_19",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_13",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net7"
},
{
"type": "source_port",
"source_port_id": "source_port_20",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_13",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_13",
"ftype": "simple_capacitor",
"name": "C50",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_21",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_14",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net8"
},
{
"type": "source_component",
"source_component_id": "source_component_14",
"ftype": "simple_chip",
"name": "X_U7",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_22",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_15",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net8"
},
{
"type": "source_port",
"source_port_id": "source_port_23",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_15",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_15",
"ftype": "simple_capacitor",
"name": "C51",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_24",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_16",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net9"
},
{
"type": "source_component",
"source_component_id": "source_component_16",
"ftype": "simple_chip",
"name": "X_W17",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_25",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_17",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net9"
},
{
"type": "source_port",
"source_port_id": "source_port_26",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_17",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_17",
"ftype": "simple_capacitor",
"name": "C52",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_board",
"source_board_id": "source_board_0",
"source_group_id": "source_group_1"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_0",
"connected_source_port_ids": [
"source_port_0",
"source_port_1"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_INTERNAL_G9",
"max_length": 6,
"display_name": ".X_G9 > .pin1 to .C44 > .pin1",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net0"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_1",
"connected_source_port_ids": [
"source_port_2"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_GROUND_G9",
"max_length": 10,
"display_name": ".C44 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_2",
"connected_source_port_ids": [
"source_port_3",
"source_port_4"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_INTERNAL_H11",
"max_length": 6,
"display_name": ".X_H11 > .pin1 to .C45 > .pin1",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net2"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_3",
"connected_source_port_ids": [
"source_port_5"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_GROUND_H11",
"max_length": 10,
"display_name": ".C45 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_4",
"connected_source_port_ids": [
"source_port_6",
"source_port_7"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_INTERNAL_H15",
"max_length": 6,
"display_name": ".X_H15 > .pin1 to .C46 > .pin1",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net3"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_5",
"connected_source_port_ids": [
"source_port_8"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_GROUND_H15",
"max_length": 10,
"display_name": ".C46 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_6",
"connected_source_port_ids": [
"source_port_9",
"source_port_10"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_INTERNAL_H17",
"max_length": 6,
"display_name": ".X_H17 > .pin1 to .C47 > .pin1",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net4"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_7",
"connected_source_port_ids": [
"source_port_11"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_GROUND_H17",
"max_length": 10,
"display_name": ".C47 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_8",
"connected_source_port_ids": [
"source_port_12",
"source_port_13"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_INTERNAL_J19",
"max_length": 6,
"display_name": ".X_J19 > .pin1 to .C48 > .pin1",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net5"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_9",
"connected_source_port_ids": [
"source_port_14"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"name": "CAP_VDDS_GROUND_J19",
"max_length": 10,
"display_name": ".C48 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "CAP_VDDS_connectivity_net1"
},
{
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},
{
"type": "pcb_port",
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"pcb_component_id": "pcb_component_9",
"layers": [
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],
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},
{
"type": "pcb_port",
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"top"
],
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},
{
"type": "pcb_port",
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"top",
"bottom",
"inner1",
"inner2"
],
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},
{
"type": "pcb_port",
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"pcb_component_id": "pcb_component_11",
"layers": [
"top"
],
"subcircuit_id": "subcircuit_source_group_0",
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},
{
"type": "pcb_port",
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"layers": [
"top"
],
"subcircuit_id": "subcircuit_source_group_0",
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},
{
"type": "pcb_port",
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"top",
"bottom",
"inner1",
"inner2"
],
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},
{
"type": "pcb_port",
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"pcb_component_id": "pcb_component_13",
"layers": [
"bottom"
],
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},
{
"type": "pcb_port",
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"layers": [
"bottom"
],
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},
{
"type": "pcb_port",
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"top",
"bottom",
"inner1",
"inner2"
],
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},
{
"type": "pcb_port",
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"top"
],
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},
{
"type": "pcb_port",
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"layers": [
"top"
],
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},
{
"type": "pcb_port",
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"top",
"bottom",
"inner1",
"inner2"
],
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},
{
"type": "pcb_port",
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"top"
],
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},
{
"type": "pcb_port",
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"layers": [
"top"
],
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},
{
"type": "pcb_trace",
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"pcb_port_2",
"fanout-exit:source_trace_1:source-0"
],
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{
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},
{
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{
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},
{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_11",
"pcb_port_11",
"fanout-exit:source_trace_7:source-0"
],
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{
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},
{
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{
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},
{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_17",
"pcb_port_17",
"fanout-exit:source_trace_11:source-0"
],
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{
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{
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_23",
"pcb_port_23",
"fanout-exit:source_trace_15:source-0"
],
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{
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},
{
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_14",
"pcb_port_14",
"fanout-exit:source_trace_9:source-0"
],
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{
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{
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_20",
"pcb_port_20",
"fanout-exit:source_trace_13:source-0"
],
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{
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{
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{
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{
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],
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},
{
"type": "pcb_trace",
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"pcb_port_8",
"pcb_port_8",
"fanout-exit:source_trace_5:source-0"
],
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{
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{
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{
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{
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],
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},
{
"type": "pcb_trace",
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"pcb_port_26",
"pcb_port_26",
"fanout-exit:source_trace_17:source-0"
],
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_5",
"pcb_port_5",
"fanout-exit:source_trace_3:source-0"
],
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{
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{
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_0",
"pcb_port_1"
],
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_4"
],
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{
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_7"
],
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{
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_10"
],
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{
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{
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{
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}
],
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},
{
"type": "pcb_trace",
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"pcb_port_13"
],
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{
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},
{
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}
],
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},
{
"type": "pcb_trace",
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"connection_name": "source_trace_10",
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"pcb_port_15",
"pcb_port_16"
],
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{
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},
{
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}
],
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},
{
"type": "pcb_trace",
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"connection_name": "source_trace_12",
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"pcb_port_18",
"pcb_port_19"
],
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{
"route_type": "wire",
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},
{
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