ShiboSoftwareDev/am625sip-linux-board

subcircuits/usb0-analog-support.tsx

import { Fragment } from "react"
import { LBZX84C6V8LT1G } from "../imports/LBZX84C6V8LT1G"

const SIGNAL_LAYERS = ["top", "inner1", "inner2", "bottom"] as const

const BoundaryPad = ({
  name,
  pcbX,
  pcbY,
  plated = false,
}: {
  name: string
  pcbX: number
  pcbY: number
  plated?: boolean
}) => (
  <chip
    name={name}
    pcbX={pcbX}
    pcbY={pcbY}
    noSchematicRepresentation
    footprint={
      <footprint>
        {plated ? (
          <platedhole
            portHints={["pin1"]}
            shape="circle"
            holeDiameter="0.3mm"
            outerDiameter="0.8mm"
          />
        ) : (
          <smtpad
            portHints={["pin1"]}
            shape="rect"
            width="0.5mm"
            height="0.5mm"
          />
        )}
      </footprint>
    }
  />
)

export const Usb0AnalogSupportSubcircuit = () => (
  <subcircuit
    name="USB0_ANALOG_SUPPORT"
    autorouter="default"
    exposedNets={["GND"]}
    defaultTraceWidth="0.15mm"
    minTraceWidth="0.08128mm"
    minTraceToPadEdgeClearance="0.05mm"
    minPadEdgeToPadEdgeClearance="0.08128mm"
    minViaEdgeToPadEdgeClearance="0.08128mm"
    minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
    minViaHoleDiameter="0.1mm"
    minViaPadDiameter="0.24mm"
  >
    <autoroutingphase
      name="USB0_ANALOG_SIGNALS"
      phaseIndex={0}
      autorouter="default"
    />
    <autoroutingphase
      name="USB0_ANALOG_GROUND_DROPS"
      phaseIndex={1}
      autorouter="fanout"
      fanoutRoutingLayers={[...SIGNAL_LAYERS]}
      fanoutPourNetMap={{ inner1: ["GND"] }}
    />

    <net name="GND" routingPhaseIndex={1} />

    <BoundaryPad name="X_SOC_VBUS" pcbX={-7} pcbY={2} />
    <BoundaryPad name="X_CONNECTOR_VBUS" pcbX={-7} pcbY={0} plated />
    <BoundaryPad name="X_RCALIB" pcbX={-7} pcbY={-2} />
    <BoundaryPad name="X_GND" pcbX={7} pcbY={-2} plated />

    <resistor
      name="R26"
      resistance="499ohm"
      footprint="0402"
      supplierPartNumbers={{ jlcpcb: ["C881065"] }}
      pcbX={-4}
      pcbY={-2}
    />
    <resistor
      name="R27"
      resistance="16.5k"
      footprint="0402"
      supplierPartNumbers={{ jlcpcb: ["C226807"] }}
      pcbX={-4}
      pcbY={2}
    />
    <resistor
      name="R28"
      resistance="3.48k"
      footprint="0402"
      supplierPartNumbers={{ jlcpcb: ["C5126222"] }}
      pcbX={-4}
      pcbY={0}
    />
    <resistor
      name="R29"
      resistance="10k"
      footprint="0402"
      supplierPartNumbers={{ jlcpcb: ["C2906861"] }}
      pcbX={-5.5}
      pcbY={1}
      pcbRotation={90}
    />
    <LBZX84C6V8LT1G name="D4" pcbX={0} pcbY={0} />

    <trace
      name="USB0_RCALIB_LOCAL"
      from=".X_RCALIB > .pin1"
      to=".R26 > .pin1"
      routingPhaseIndex={0}
    />
    <trace
      name="USB0_VBUS_SOC_NODE"
      path={[".X_SOC_VBUS > .pin1", ".R27 > .pin1", ".R29 > .pin1"]}
      routingPhaseIndex={0}
    />
    <trace
      name="USB0_VBUS_DIVIDER_NODE"
      path={[".R27 > .pin2", ".R28 > .pin2", ".D4 > .cathode"]}
      routingPhaseIndex={0}
    />
    <trace
      name="USB0_VBUS_SOURCE"
      from=".R28 > .pin1"
      to=".X_CONNECTOR_VBUS > .pin1"
      width="0.3mm"
      routingPhaseIndex={0}
    />

    {[
      ["USB0_RCALIB_GND", ".R26 > .pin2"],
      ["USB0_VBUS_PULLDOWN_GND", ".R29 > .pin2"],
      ["USB0_VBUS_CLAMP_GND", ".D4 > .anode"],
      ["USB0_ANALOG_BOUNDARY_GND", ".X_GND > .pin1"],
    ].map(([name, from]) => (
      <Fragment key={name}>
        <trace
          name={name}
          from={from}
          to="net.GND"
          width="0.3mm"
          routingPhaseIndex={1}
        />
      </Fragment>
    ))}
  </subcircuit>
)

export default () => (
  <board
    width="18mm"
    height="10mm"
    layers={4}
    defaultTraceWidth="0.15mm"
    minTraceWidth="0.08128mm"
    minTraceToPadEdgeClearance="0.05mm"
    minPadEdgeToPadEdgeClearance="0.08128mm"
    minViaEdgeToPadEdgeClearance="0.08128mm"
    minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
    minViaHoleDiameter="0.1mm"
    minViaPadDiameter="0.24mm"
    pcbStyle={{ viaHoleDiameter: "0.1mm", viaPadDiameter: "0.24mm" }}
    autorouter="default"
  >
    <Usb0AnalogSupportSubcircuit />
  </board>
)