ShiboSoftwareDev/am625sip-linux-board
This code defines the physical footprint and pin layout for an AM625 System-in-Package (SIP) component, detailing pad positions, pin labels, and package outline for hardware integration.
- Version
- 1.0.24
- License
- unset
- Stars
- 0
subcircuits/usb0-data-esd.tsx
import { ESD122DMXR } from "../imports/ESD122DMXR"
const BoundaryPad = ({
name,
pcbX,
pcbY,
plated = false,
}: {
name: string
pcbX: number
pcbY: number
plated?: boolean
}) => (
<chip
name={name}
pcbX={pcbX}
pcbY={pcbY}
noSchematicRepresentation
footprint={
<footprint>
{plated ? (
<platedhole
portHints={["pin1"]}
shape="circle"
holeDiameter="0.3mm"
outerDiameter="0.8mm"
/>
) : (
<smtpad
portHints={["pin1"]}
shape="rect"
width="0.3mm"
height="0.3mm"
/>
)}
</footprint>
}
/>
)
export const Usb0DataEsdSubcircuit = () => (
<subcircuit
name="USB0_DATA_ESD"
autorouter="default"
defaultTraceWidth="0.08128mm"
minTraceWidth="0.08128mm"
minTraceToPadEdgeClearance="0.05mm"
minPadEdgeToPadEdgeClearance="0.08128mm"
minViaEdgeToPadEdgeClearance="0.08128mm"
minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
minViaHoleDiameter="0.1mm"
minViaPadDiameter="0.24mm"
>
<autoroutingphase
name="USB0_ESD_DATA_PAIR"
phaseIndex={0}
autorouter="default"
/>
<autoroutingphase
name="USB0_ESD_GROUND_LINK"
phaseIndex={1}
autorouter="default"
/>
<BoundaryPad name="X_SOC_DP" pcbX={-2} pcbY={0.4} />
<BoundaryPad name="X_SOC_DM" pcbX={-2} pcbY={-0.4} />
<BoundaryPad name="X_CONNECTOR_DP" pcbX={2} pcbY={0.4} />
<BoundaryPad name="X_CONNECTOR_DM" pcbX={2} pcbY={-0.4} />
<BoundaryPad name="X_GND" pcbX={0} pcbY={-1.5} plated />
<ESD122DMXR name="U5" pcbX={0} pcbY={0} />
<bus
name="USB0_ESD_PROTECTED_PAIR"
connections={["USB0_ESD_DP", "USB0_ESD_DM"]}
routingPhaseIndex={0}
maxLengthSkew="0.15mm"
targetImpedance="45ohm"
pcbTraceWidth="0.15mm"
preferredLayer="top"
pcbAllowedLayers={["top"]}
/>
<trace
name="USB0_ESD_DP"
path={[
".X_SOC_DP > .pin1",
".U5 > .IO2",
".X_CONNECTOR_DP > .pin1",
]}
width="0.15mm"
routingPhaseIndex={0}
/>
<trace
name="USB0_ESD_DM"
path={[
".X_SOC_DM > .pin1",
".U5 > .IO1",
".X_CONNECTOR_DM > .pin1",
]}
width="0.15mm"
routingPhaseIndex={0}
/>
<trace
name="USB0_ESD_LOCAL_GROUND"
from=".U5 > .GND"
to=".X_GND > .pin1"
width="0.3mm"
routingPhaseIndex={1}
/>
</subcircuit>
)
export default () => (
<board
width="6mm"
height="5mm"
layers={4}
defaultTraceWidth="0.08128mm"
minTraceWidth="0.08128mm"
minTraceToPadEdgeClearance="0.05mm"
minPadEdgeToPadEdgeClearance="0.08128mm"
minViaEdgeToPadEdgeClearance="0.08128mm"
minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
minViaHoleDiameter="0.1mm"
minViaPadDiameter="0.24mm"
pcbStyle={{ viaHoleDiameter: "0.1mm", viaPadDiameter: "0.24mm" }}
autorouter="default"
>
<Usb0DataEsdSubcircuit />
</board>
)