ShiboSoftwareDev/t113-s3-linux-computer-p9
The code defines a PCB subcircuit for a buck converter module featuring a TMI3112H IC, FTC252010S power switch, and associated passive components like capacitors and resistors for voltage regulation and feedback control.
- Version
- 0.1.4
- License
- unset
- Stars
- 0
subcircuits/soc-core.tsx
import { Fragment } from "react"
import { T113_S3 } from "../imports/T113_S3"
import { TLV803SDBZR } from "../imports/TLV803SDBZR"
import { TS342A2P_WZ } from "../imports/TS342A2P_WZ"
import { X322524MOB4SI } from "../imports/X322524MOB4SI"
import { C, R, cleanImportedSilk, part } from "../components/standard-passives"
const SECTION = "SOC_CORE"
const signalPins = [
{ pin: 1, label: "PG6", net: "HDMI_RESET_N" },
{ pin: 2, label: "PG7", net: "HDMI_INT_N" },
{ pin: 3, label: "PG8", net: "RGB_LED_R" },
{ pin: 4, label: "PG9", net: "RGB_LED_G" },
{ pin: 5, label: "PG10", net: "RGB_LED_B" },
{ pin: 6, label: "PG11", net: "I2S1_MCLK" },
{ pin: 7, label: "PF0", net: "SD_DAT1" },
{ pin: 8, label: "PF1", net: "SD_DAT0" },
{ pin: 9, label: "PF2", net: "SD_CLK" },
{ pin: 10, label: "PF3", net: "SD_CMD" },
{ pin: 11, label: "PF4", net: "SD_DAT3" },
{ pin: 12, label: "PF5", net: "SD_DAT2" },
{ pin: 13, label: "PF6", net: "SD_CARD_DETECT_N" },
{ pin: 14, label: "PC7", net: "SPI0_HOLD" },
{ pin: 15, label: "PC6", net: "SPI0_WP" },
{ pin: 16, label: "PC5", net: "SPI0_MISO" },
{ pin: 17, label: "PC4", net: "SPI0_MOSI" },
{ pin: 18, label: "PC3", net: "SPI0_CS_N" },
{ pin: 19, label: "PC2", net: "SPI0_SCLK" },
{ pin: 31, label: "PE13", net: "I2C2_SDA" },
{ pin: 32, label: "PE12", net: "I2C2_SCL" },
{ pin: 33, label: "PE3", net: "UART0_RX" },
{ pin: 35, label: "PE2", net: "UART0_TX" },
{ pin: 36, label: "PE11", net: "JTAG_TCK" },
{ pin: 37, label: "PE10", net: "JTAG_TDO" },
{ pin: 38, label: "PE9", net: "JTAG_TDI" },
{ pin: 39, label: "PE8", net: "JTAG_TMS" },
{ pin: 41, label: "PE6", net: "GPIO_PE6" },
{ pin: 42, label: "PE5", net: "GPIO_PE5" },
{ pin: 43, label: "PE4", net: "GPIO_PE4" },
{ pin: 53, label: "PD21", net: "LCD_VSYNC" },
{ pin: 54, label: "PD20", net: "LCD_HSYNC" },
{ pin: 55, label: "PD0", net: "LCD_D2" },
{ pin: 56, label: "PD1", net: "LCD_D3" },
{ pin: 57, label: "PD2", net: "LCD_D4" },
{ pin: 58, label: "PD3", net: "LCD_D5" },
{ pin: 59, label: "PD4", net: "LCD_D6" },
{ pin: 60, label: "PD5", net: "LCD_D7" },
{ pin: 61, label: "PD6", net: "LCD_D10" },
{ pin: 62, label: "PD7", net: "LCD_D11" },
{ pin: 63, label: "PD8", net: "LCD_D12" },
{ pin: 64, label: "PD9", net: "LCD_D13" },
{ pin: 67, label: "PD10", net: "LCD_D14" },
{ pin: 68, label: "PD11", net: "LCD_D15" },
{ pin: 69, label: "PD13", net: "LCD_D19" },
{ pin: 70, label: "PD12", net: "LCD_D18" },
{ pin: 71, label: "PD14", net: "LCD_D20" },
{ pin: 72, label: "PD15", net: "LCD_D21" },
{ pin: 73, label: "PD16", net: "LCD_D22" },
{ pin: 74, label: "PD17", net: "LCD_D23" },
{ pin: 75, label: "PD18", net: "LCD_PCLK" },
{ pin: 76, label: "PD19", net: "LCD_DE" },
{ pin: 79, label: "PB7", net: "LCD_D17" },
{ pin: 80, label: "PB6", net: "LCD_D16" },
{ pin: 82, label: "PB5", net: "LCD_D9" },
{ pin: 84, label: "PB4", net: "LCD_D8" },
{ pin: 85, label: "PB3", net: "LCD_D1" },
{ pin: 86, label: "PB2", net: "LCD_D0" },
{ pin: 114, label: "USB0_DM", net: "USB0_DM" },
{ pin: 115, label: "USB0_DP", net: "USB0_DP" },
{ pin: 124, label: "PG12", net: "I2S1_LRCK" },
{ pin: 125, label: "PG13", net: "I2S1_BCLK" },
{ pin: 127, label: "PG15", net: "I2S1_DOUT0" },
] as const
const decouplers = [
{ name: "C_PLL", pin: "VCC_PLL", net: "VDD18_SOC", x: 1.4, y: -9.7, rotation: 270 },
{ name: "C_RTC", pin: "VCC_RTC", net: "VDD18_SOC", x: 3.8, y: -10.3, rotation: 270 },
{ name: "C_PE", pin: "VCC_PE", net: "VDD_3V3", x: 9.8, y: -5.4 },
{ name: "C_SYS0", pin: "VDD_SYS0", net: "VCORE_0V9", x: 12.0, y: -3.0, rotation: 270 },
{ name: "C_DRAM0", pin: "VCC_DRAM0", net: "VDRAM_1V5", x: 11.95, y: -0.2, rotation: 90 },
{ name: "C_DRAM1", pin: "VCC_DRAM1", net: "VDRAM_1V5", x: 9.3, y: 0.0, rotation: 0 },
{ name: "C_DRAM18", pin: "VDD18_DRAM", net: "VDD18_SOC", x: 9.3, y: 1.7, rotation: 0 },
{ name: "C_SYS1", pin: "VDD_SYS1", net: "VCORE_0V9", x: 9.3, y: 4.0, rotation: 90 },
{ name: "C_LVDS", pin: "VCC_LVDS", net: "VDD18_SOC", x: 5.5, y: 10.2 },
{ name: "C_PD", pin: "VCC_PD", net: "VDD_3V3", x: 3.8, y: 10.2, rotation: 90 },
{ name: "C_TVOUT", pin: "VCC_TVOUT", net: "VDD_3V3", x: 2.1, y: 10.2, rotation: 90 },
{ name: "C_SYS2", pin: "VDD_SYS2", net: "VCORE_0V9", x: 0.4, y: 10.2, rotation: 90 },
{ name: "C_IO", pin: "VCC_IO", net: "VDD_3V3", x: -1.3, y: 10.2, rotation: 90 },
{ name: "C_AVCC", pin: "AVCC", net: "VDD18_SOC", x: -3.5, y: 10.2 },
{ name: "C_HPVCC", pin: "HPVCC", net: "VDD18_SOC", x: -6.6, y: 10.2 },
{ name: "C_TVIN", pin: "VCC_TVIN", net: "VDD18_SOC", x: -9.8, y: 2.2 },
{ name: "C_CORE0", pin: "VDD_CORE0", net: "VCORE_0V9", x: -9.8, y: -1.4 },
{ name: "C_CORE1", pin: "VDD_CORE1", net: "VCORE_0V9", x: -9.8, y: -3.0 },
{ name: "C_PG", pin: "VCC_PG", net: "VDD_3V3", x: -9.8, y: -5.8 },
] as const
const powerPlanePhase = {
VDD18_SOC: -145,
VDD_3V3: -144,
VDRAM_1V5: -143,
VCORE_0V9: -142,
} as const
const vdd33Feeds = [
{ cap: "C_PE", pin: "VCC_PE", x: 11.8, y: -5.4, rotation: 90 },
{ cap: "C_PD", pin: "VCC_PD", x: 3.8, y: 12.0, rotation: 0 },
{ cap: "C_TVOUT", pin: "VCC_TVOUT", x: 2.1, y: 12.0, rotation: 0 },
{ cap: "C_IO", pin: "VCC_IO", x: -1.3, y: 13.5, rotation: 0 },
{ cap: "C_PG", pin: "VCC_PG", x: -12.0, y: -5.8, rotation: 90 },
] as const
const vdd18Feeds = [
{ cap: "C_PLL", pin: "VCC_PLL", x: -1.0, y: -13.0, rotation: 270, localPin: "pin1", planePin: "pin2" },
{ cap: "C_RTC", pin: "VCC_RTC", x: 5.2, y: -10.0, rotation: 0, localPin: "pin1", planePin: "pin2" },
{ cap: "C_DRAM18", pin: "VDD18_DRAM", x: 11.1, y: 1.7, rotation: 0, localPin: "pin1", planePin: "pin2" },
{ cap: "C_LVDS", pin: "VCC_LVDS", x: 7.3, y: 10.2, rotation: 0, localPin: "pin1", planePin: "pin2" },
{ cap: "C_AVCC", pin: "AVCC", x: -3.5, y: 12.0, rotation: 90, localPin: "pin1", planePin: "pin2" },
{ cap: "C_HPVCC", pin: "HPVCC", x: -8.4, y: 10.2, rotation: 0, localPin: "pin2", planePin: "pin1" },
{ cap: "C_TVIN", pin: "VCC_TVIN", x: -11.6, y: 2.2, rotation: 0, localPin: "pin2", planePin: "pin1" },
] as const
const groundFanoutPhases = Array.from({ length: 34 }, (_, index) => -130 + index)
const throughViaLayers: Array<"top" | "inner1" | "inner2" | "inner3" | "inner4" | "inner5" | "inner6" | "inner7" | "inner8" | "bottom"> =
["top", "inner1", "inner2", "inner3", "inner4", "inner5", "inner6", "inner7", "inner8", "bottom"]
const vdd18PlanePhaseByCapName: Record<string, number> = {
C_PLL: -145.9,
C_RTC: -145.8,
C_DRAM18: -145.7,
C_LVDS: -145.6,
C_AVCC: -145.5,
C_HPVCC: -145.4,
C_TVIN: -145.3,
}
const vdd18LocalPhaseByCapName: Record<string, number> = {
C_PLL: -149.8,
C_RTC: -149.76,
C_DRAM18: -149.72,
C_LVDS: -149.68,
C_AVCC: -149.64,
C_HPVCC: -149.6,
C_TVIN: -149.56,
}
const vdd18FanoutPhases = [-145.9, -145.8, -145.7, -145.6, -145.5, -145.4, -145.3, -145.2, -145.1, -145]
const vdd33PlanePhaseByCapName: Record<string, number> = {
C_PE: -144.9,
C_PD: -144.8,
C_TVOUT: -144.7,
C_IO: -144.6,
C_PG: -144.5,
}
const vdd33FanoutPhases = [-144.9, -144.8, -144.7, -144.6, -144.5, -144.4, -144.3, -144.2]
const vdramFanoutPhases = [-143.9, -143.8, -143.7]
const vcoreFanoutPhaseByName: Record<string, number> = {
SYS0: -142.9,
SYS1: -142.8,
SYS2: -142.7,
CORE0: -142.6,
CORE1: -142.5,
}
const vcoreFanoutPhases = [-142.9, -142.8, -142.7, -142.6, -142.5]
export const SocCoreSubcircuit = ({ exposePeripheralSignals = true }: { exposePeripheralSignals?: boolean } = {}) => (
<subcircuit name="SOC_CORE" width="60mm" height="58mm" autorouter="default"
autorouterVersion="beta_pipeline9" autorouterEffortLevel="10x" defaultTraceWidth="0.15mm"
exposeNets schAutoLayoutEnabled schTraceAutoLabelEnabled>
<net name="VDD18_SOC" isPowerNet routingPhaseIndex={-145} nominalTraceWidth="0.20mm" />
<net name="VDD_3V3" isPowerNet routingPhaseIndex={-144} nominalTraceWidth="0.20mm" />
<net name="VDRAM_1V5" isPowerNet routingPhaseIndex={-143} nominalTraceWidth="0.20mm" />
<net name="VCORE_0V9" isPowerNet routingPhaseIndex={-142} nominalTraceWidth="0.20mm" />
<net name="GND" isGroundNet routingPhaseIndex={-130} nominalTraceWidth="0.25mm" />
{vdd18FanoutPhases.map((phaseIndex) => <Fragment key={`vdd18-fanout-${phaseIndex}`}>
<autoroutingphase name={`VDD18_PLANE_FANOUT_${phaseIndex}`} phaseIndex={phaseIndex} autorouter="fanout"
fanoutBoundaryPadding="3mm" fanoutRoutingLayers={throughViaLayers}
fanoutPourNetMap={{ inner1: "VDD18_SOC" }} />
</Fragment>)}
{vdd33FanoutPhases.map((phaseIndex) => <Fragment key={`vdd33-fanout-${phaseIndex}`}>
<autoroutingphase name={`VDD33_PLANE_FANOUT_${phaseIndex}`} phaseIndex={phaseIndex} autorouter="fanout"
fanoutBoundaryPadding="3mm" fanoutRoutingLayers={throughViaLayers}
fanoutPourNetMap={{ inner2: "VDD_3V3" }} />
</Fragment>)}
{vdramFanoutPhases.map((phaseIndex) => <Fragment key={`vdram-fanout-${phaseIndex}`}>
<autoroutingphase name={`VDRAM_PLANE_FANOUT_${phaseIndex}`} phaseIndex={phaseIndex} autorouter="fanout"
fanoutBoundaryPadding="3mm" fanoutRoutingLayers={throughViaLayers}
fanoutPourNetMap={{ inner3: "VDRAM_1V5" }} />
</Fragment>)}
{vcoreFanoutPhases.map((phaseIndex) => <Fragment key={`vcore-fanout-${phaseIndex}`}>
<autoroutingphase name={`VCORE_PLANE_FANOUT_${phaseIndex}`} phaseIndex={phaseIndex} autorouter="fanout"
fanoutBoundaryPadding="3mm" fanoutRoutingLayers={throughViaLayers}
fanoutPourNetMap={{ inner4: "VCORE_0V9" }} />
</Fragment>)}
{groundFanoutPhases.map((phaseIndex) => <Fragment key={`ground-fanout-${phaseIndex}`}>
<autoroutingphase name={`GROUND_PLANE_FANOUT_${phaseIndex}`}
phaseIndex={phaseIndex} autorouter="fanout"
fanoutBoundaryPadding={phaseIndex === -109 ? "4mm" : "3mm"} fanoutRoutingLayers={throughViaLayers}
fanoutPourNetMap={{ inner5: "GND" }} />
</Fragment>)}
<bus name="VCORE_SYS1_TOP" connections={["VCORE_SYS1_DECOUPLE", "VCORE_SYS1_DISTRIBUTE"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-148} />
<bus name="VCORE_SYS2_TOP" connections={["VCORE_SYS2_DECOUPLE", "VCORE_SYS2_DISTRIBUTE"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-148} />
<bus name="VCORE_CORE0_TOP" connections={["VCORE_CORE0_DECOUPLE", "VCORE_CORE0_DISTRIBUTE"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-148} />
<bus name="VCORE_CORE1_TOP" connections={["VCORE_CORE1_DECOUPLE", "VCORE_CORE1_DISTRIBUTE"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-148} />
{vdd18Feeds.map(({ cap }) => <Fragment key={`vdd18-local-buses-${cap}`}>
{cap === "C_RTC" ? null : <>
<bus name={`${cap}_DECOUPLE_TOP`} connections={[`${cap}_DECOUPLE`]}
pcbAllowedLayers={["top"]} routingPhaseIndex={vdd18LocalPhaseByCapName[cap]} />
{cap === "C_DRAM18" ? null : <bus name={`${cap}_DISTRIBUTE_TOP`} connections={[`${cap}_DISTRIBUTE`]}
pcbAllowedLayers={["top"]} routingPhaseIndex={vdd18LocalPhaseByCapName[cap] + 0.01} />}
</>}
</Fragment>)}
<bus name="LDO_INPUT_DECOUPLE_TOP" connections={["LDO_INPUT_DECOUPLE"]}
pcbAllowedLayers={["top"]} routingPhaseIndex={-149.5} />
<bus name="LDO_INPUT_DISTRIBUTE_TOP" connections={["LDO_INPUT_DISTRIBUTE"]}
pcbAllowedLayers={["top"]} routingPhaseIndex={-149.49} />
<bus name="RESET_LOCAL_TOP" connections={["SOC_RESET_LOCAL"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-149.9} />
<bus name="RESET_SUPERVISOR_TO_FILTER_TOP" connections={["RESET_SUPERVISOR_TO_FILTER"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-149.89} />
<bus name="RESET_FILTER_TO_PULLUP_TOP" connections={["RESET_FILTER_TO_PULLUP"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-149.88} />
<bus name="RESET_FILTER_TO_ISO_TOP" connections={["RESET_FILTER_TO_ISO"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-149.87} />
<bus name="BOOT_SEL0_TO_SOC_TOP" connections={["BOOT_SEL0_TO_SOC"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-149.48} />
<bus name="BOOT_SEL1_TO_SOC_TOP" connections={["BOOT_SEL1_TO_SOC"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-149.47} />
<bus name="VDRAM0_DISTRIBUTE_TOP" connections={["VDRAM0_DISTRIBUTE"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-152.3} />
<bus name="VDRAM1_DECOUPLE_TOP" connections={["VDRAM1_DECOUPLE"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-152.2} />
<T113_S3 {...cleanImportedSilk} name="U_SOC" pcbX={0} pcbY={0} schSectionName={SECTION}
schWidth={16} schHeight={19}
noConnect={["REFCLK_OUT", "X32KIN", "X32KOUT", "PD22", "PE7", "PE0", "PE1", "TVOUT0", "MICIN3P", "MICIN3N", "VRA2", "VRA1", "FMINR", "FMINL", "LINEINR", "LINEINL", "HPOUTR", "HPOUTL", "HPOUTFB", "GPADC0", "TP_X1", "TP_X2", "TP_Y1", "TP_Y2", "NC0", "TVIN0", "TVIN1", "TVIN_VRP", "TVIN_VRN", "USB1_DP", "USB1_DM", "PG1", "PG2", "PG0", "PG3", "PG5", "PG4", "PG14", ...(exposePeripheralSignals ? [] : signalPins.filter(({ label }) => label !== "PC4" && label !== "PC5").map(({ label }) => label))]} />
{exposePeripheralSignals && signalPins.map(({ label, net }) => <Fragment key={`route-${net}`}>
<trace name={`SOC_${net}`} from={`.U_SOC > .${label}`} to={`net.${net}`} />
</Fragment>)}
<trace from=".U_SOC > .AGND" to="net.GND" width="0.35mm" maxLength="15mm" routingPhaseIndex={-111} />
<trace from=".U_SOC > .EPAD" to="net.GND" width="0.6mm" maxLength="15mm" routingPhaseIndex={-110} />
{decouplers.map((decoupler, index) => {
const { name, pin, net, x, y } = decoupler
const rotation = "rotation" in decoupler ? decoupler.rotation : 0
return <Fragment key={name}>
<C name={name} capacitance={part.c100n.value} mpn={part.c100n.mpn} lcsc={part.c100n.lcsc}
x={x} y={y} rotation={rotation} sectionName={SECTION} />
<trace name={`${name}_GROUND`} from={`.${name} > .pin2`} to="net.GND" maxLength="8mm"
routingPhaseIndex={-130 + index} />
</Fragment>
})}
{vdd18Feeds.map(({ cap, pin, x, y, rotation, localPin, planePin }) => <Fragment key={`feed-${cap}`}>
<R name={`R_${cap}_FEED`} resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={x} y={y} rotation={rotation} sectionName={SECTION} />
{cap === "C_RTC" ?
<trace name="C_RTC_LOCAL" path={[`.U_SOC > .${pin}`, `.${cap} > .pin1`, `.R_${cap}_FEED > .${localPin}`]}
width="0.15mm" maxLength="12mm" routingPhaseIndex={vdd18LocalPhaseByCapName[cap]} /> : <>
<trace name={`${cap}_DECOUPLE`} from={`.U_SOC > .${pin}`} to={`.${cap} > .pin1`}
width="0.15mm" maxLength="10mm" maxViaCount={0} routingPhaseIndex={vdd18LocalPhaseByCapName[cap]} />
<trace name={`${cap}_DISTRIBUTE`} from={`.${cap} > .pin1`} to={`.R_${cap}_FEED > .${localPin}`}
width="0.15mm" maxLength="8mm" maxViaCount={cap === "C_DRAM18" ? undefined : 0}
routingPhaseIndex={vdd18LocalPhaseByCapName[cap] + 0.01} />
</>}
<trace name={`${cap}_PLANE`} from={`.R_${cap}_FEED > .${planePin}`} to="net.VDD18_SOC"
width="0.35mm" maxLength="15mm" routingPhaseIndex={vdd18PlanePhaseByCapName[cap]} />
</Fragment>)}
<R name="R_VCORE_SYS0" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={13.4} y={-2.57} rotation={0} sectionName={SECTION} />
<R name="R_VCORE_SYS1" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={10.7} y={3.57} rotation={0} sectionName={SECTION} />
<R name="R_VCORE_SYS2" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={0.4} y={12.0} rotation={0} sectionName={SECTION} />
<R name="R_VCORE_CORE0" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={-12.0} y={-1.4} rotation={90} sectionName={SECTION} />
<R name="R_VCORE_CORE1" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={-12.0} y={-3.0} rotation={90} sectionName={SECTION} />
<trace name="VCORE_SYS0_DECOUPLE" from=".U_SOC > .VDD_SYS0" to=".C_SYS0 > .pin1" width="0.15mm" maxLength="10mm" routingPhaseIndex={-148} />
<trace name="VCORE_SYS0_DISTRIBUTE" from=".C_SYS0 > .pin1" to=".R_VCORE_SYS0 > .pin1" width="0.15mm" maxLength="10mm" routingPhaseIndex={-148} />
<trace name="VCORE_SYS1_DECOUPLE" from=".U_SOC > .VDD_SYS1" to=".C_SYS1 > .pin1" width="0.15mm" maxLength="15mm" routingPhaseIndex={-148} />
<trace name="VCORE_SYS1_DISTRIBUTE" from=".C_SYS1 > .pin1" to=".R_VCORE_SYS1 > .pin1" width="0.15mm" maxLength="10mm" routingPhaseIndex={-148} />
<trace name="VCORE_SYS0_FEED" from="R_VCORE_SYS0.pin2" to="net.VCORE_0V9" width="0.35mm" maxLength="40mm" routingPhaseIndex={vcoreFanoutPhaseByName.SYS0} />
<trace name="VCORE_SYS1_FEED" from="R_VCORE_SYS1.pin2" to="net.VCORE_0V9" width="0.35mm" maxLength="40mm" routingPhaseIndex={vcoreFanoutPhaseByName.SYS1} />
<trace name="VCORE_SYS2_DECOUPLE" from=".U_SOC > .VDD_SYS2" to=".C_SYS2 > .pin1" width="0.15mm" maxLength="6mm" routingPhaseIndex={-148} />
<trace name="VCORE_SYS2_DISTRIBUTE" from=".C_SYS2 > .pin1" to=".R_VCORE_SYS2 > .pin1" width="0.15mm" maxLength="8mm" routingPhaseIndex={-148} />
<trace name="VCORE_SYS2_FEED" from="R_VCORE_SYS2.pin2" to="net.VCORE_0V9" width="0.35mm" maxLength="40mm" routingPhaseIndex={vcoreFanoutPhaseByName.SYS2} />
<trace name="VCORE_CORE0_DECOUPLE" from=".U_SOC > .VDD_CORE0" to=".C_CORE0 > .pin1" width="0.15mm" maxLength="6mm" routingPhaseIndex={-148} />
<trace name="VCORE_CORE0_DISTRIBUTE" from=".C_CORE0 > .pin1" to=".R_VCORE_CORE0 > .pin1" width="0.15mm" maxLength="8mm" routingPhaseIndex={-148} />
<trace name="VCORE_CORE1_DECOUPLE" from=".U_SOC > .VDD_CORE1" to=".C_CORE1 > .pin1" width="0.15mm" maxLength="6mm" routingPhaseIndex={-148} />
<trace name="VCORE_CORE1_DISTRIBUTE" from=".C_CORE1 > .pin1" to=".R_VCORE_CORE1 > .pin1" width="0.15mm" maxLength="8mm" routingPhaseIndex={-148} />
<trace name="VCORE_CORE0_FEED" from="R_VCORE_CORE0.pin2" to="net.VCORE_0V9" width="0.35mm" maxLength="40mm" routingPhaseIndex={vcoreFanoutPhaseByName.CORE0} />
<trace name="VCORE_CORE1_FEED" from="R_VCORE_CORE1.pin2" to="net.VCORE_0V9" width="0.35mm" maxLength="40mm" routingPhaseIndex={vcoreFanoutPhaseByName.CORE1} />
<R name="R_VDRAM0" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={13.3} y={-0.63} rotation={0} sectionName={SECTION} />
<R name="R_VDRAM1" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={12.5} y={4.0} rotation={0} sectionName={SECTION} />
<trace name="VDRAM0_DECOUPLE" from=".U_SOC > .VCC_DRAM0" to=".C_DRAM0 > .pin1"
width="0.15mm" maxLength="8mm" routingPhaseIndex={-152.4} />
<trace name="VDRAM0_DISTRIBUTE" from=".C_DRAM0 > .pin1" to=".R_VDRAM0 > .pin1"
width="0.15mm" maxLength="8mm" maxViaCount={0} routingPhaseIndex={-152.3} />
<trace name="VDRAM0_FEED" from="R_VDRAM0.pin2" to="net.VDRAM_1V5" width="0.35mm" maxLength="40mm" routingPhaseIndex={-143.9} />
<trace name="VDRAM1_DECOUPLE" from=".U_SOC > .VCC_DRAM1" to=".C_DRAM1 > .pin1"
width="0.15mm" maxLength="8mm" maxViaCount={0} routingPhaseIndex={-152.2} />
<trace name="VDRAM1_DISTRIBUTE" from=".C_DRAM1 > .pin1" to=".R_VDRAM1 > .pin1"
width="0.15mm" maxLength="20mm" routingPhaseIndex={-152.1} />
<trace name="VDRAM1_FEED" from="R_VDRAM1.pin2" to="net.VDRAM_1V5" width="0.35mm" maxLength="40mm" routingPhaseIndex={-143.8} />
{vdd33Feeds.map(({ cap, pin, x, y, rotation }) => <Fragment key={`feed-${cap}`}>
<R name={`R_${cap}_FEED`} resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={x} y={y} rotation={rotation} sectionName={SECTION} />
<trace name={`${cap}_DECOUPLE`} from={`.U_SOC > .${pin}`} to={`.${cap} > .pin1`}
width="0.15mm" maxLength="8mm" routingPhaseIndex={-149} />
<trace name={`${cap}_DISTRIBUTE`} from={`.${cap} > .pin1`} to={`.R_${cap}_FEED > .pin1`}
width="0.15mm" maxLength="8mm" routingPhaseIndex={-149} />
<trace name={`${cap}_FEED`} from={`.R_${cap}_FEED > .pin2`} to="net.VDD_3V3"
width="0.35mm" maxLength="50mm" routingPhaseIndex={vdd33PlanePhaseByCapName[cap]} />
</Fragment>)}
<C name="C_LDO_IN" capacitance={part.c1u.value} mpn={part.c1u.mpn} lcsc={part.c1u.lcsc}
x={6.95} y={-11.5} rotation={270} sectionName={SECTION} />
<R name="R_LDO_INPUT_FEED" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={8.3} y={-11.07} rotation={0} sectionName={SECTION} />
<trace name="LDO_INPUT_DECOUPLE" from="U_SOC.LDO_IN" to="C_LDO_IN.pin1"
width="0.20mm" maxLength="8mm" maxViaCount={0} routingPhaseIndex={-149.5} />
<trace name="LDO_INPUT_DISTRIBUTE" from="C_LDO_IN.pin1" to="R_LDO_INPUT_FEED.pin1"
width="0.20mm" maxLength="5mm" maxViaCount={0} routingPhaseIndex={-149.49} />
<trace name="LDO_INPUT_PLANE" from="R_LDO_INPUT_FEED.pin2" to="net.VDD_3V3" width="0.35mm" maxLength="30mm" routingPhaseIndex={-144.4} />
<trace from="C_LDO_IN.pin2" to="net.GND" width="0.35mm" maxLength="15mm" routingPhaseIndex={-109} />
<C name="C_LDOA_OUT" capacitance={part.c4u7.value} mpn={part.c4u7.mpn} lcsc={part.c4u7.lcsc} size="0603" x={10.2} y={-7.8} rotation={90} sectionName={SECTION} />
<C name="C_LDOB_OUT" capacitance={part.c4u7.value} mpn={part.c4u7.mpn} lcsc={part.c4u7.lcsc} size="0603" x={10.2} y={-10.5} rotation={90} sectionName={SECTION} />
<R name="R_VDD18_SOURCE" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={12.0} y={-7.8} rotation={90} sectionName={SECTION} />
<R name="R_VDRAM_SOURCE" resistance={part.r0.value} mpn={part.r0.mpn} lcsc={part.r0.lcsc}
x={12.0} y={-10.5} rotation={90} sectionName={SECTION} />
<trace name="LDOA_LOCAL_CAP" from="C_LDOA_OUT.pin1" to="U_SOC.LDOA_OUT" width="0.20mm" maxLength="12mm" routingPhaseIndex={-146} />
<trace name="LDOA_SOURCE_LOCAL" from="C_LDOA_OUT.pin1" to="R_VDD18_SOURCE.pin1" width="0.25mm" maxLength="8mm" routingPhaseIndex={-146} />
<trace name="LDOA_PLANE" from="R_VDD18_SOURCE.pin2" to="net.VDD18_SOC" width="0.45mm" maxLength="15mm" routingPhaseIndex={-145.2} />
<trace from="C_LDOA_OUT.pin2" to="net.GND" width="0.35mm" maxLength="15mm" routingPhaseIndex={-108} />
<trace name="LDOB_LOCAL_CAP" from="C_LDOB_OUT.pin1" to="U_SOC.LDOB_OUT" width="0.20mm" maxLength="12mm" routingPhaseIndex={-146} />
<trace name="LDOB_SOURCE_LOCAL" from="C_LDOB_OUT.pin1" to="R_VDRAM_SOURCE.pin1" width="0.25mm" maxLength="8mm" routingPhaseIndex={-146} />
<trace name="LDOB_PLANE" from="R_VDRAM_SOURCE.pin2" to="net.VDRAM_1V5" width="0.45mm" maxLength="30mm" routingPhaseIndex={-143.7} />
<trace from="C_LDOB_OUT.pin2" to="net.GND" width="0.35mm" maxLength="15mm" routingPhaseIndex={-107} />
<R name="R_DRAM_ZQ" resistance={part.r240.value} mpn={part.r240.mpn} lcsc={part.r240.lcsc} x={9.3} y={-1.5} rotation={270} sectionName={SECTION} />
<trace name="DRAM_ZQ_LOCAL" from=".U_SOC > .DZQ" to="R_DRAM_ZQ.pin1" maxLength="12mm" maxViaCount={0} routingPhaseIndex={-151} />
<bus name="DRAM_ZQ_TOP_LAYER" connections={["DRAM_ZQ_LOCAL"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-151} />
<trace from="R_DRAM_ZQ.pin2" to="net.GND" maxLength="15mm" routingPhaseIndex={-106} />
<X322524MOB4SI {...cleanImportedSilk} name="X1" pcbX={2.4} pcbY={-14.1} pcbRotation={180} schSectionName={SECTION} />
<C name="C_X24_IN" capacitance={part.c20p.value} mpn={part.c20p.mpn} lcsc={part.c20p.lcsc} x={5.2} y={-11.3} rotation={0} sectionName={SECTION} />
<C name="C_X24_OUT" capacitance={part.c20p.value} mpn={part.c20p.mpn} lcsc={part.c20p.lcsc} x={1.3} y={-17.1} rotation={270} sectionName={SECTION} />
<trace name="X24_DXOUT_SIGNAL" from=".U_SOC > .DXOUT" to="X1.pin3"
maxLength="10mm" maxViaCount={0} routingPhaseIndex={-150.4} />
<trace name="X24_DXOUT_LOAD" from="X1.pin3" to="C_X24_OUT.pin1"
maxLength="4mm" maxViaCount={0} routingPhaseIndex={-150.3} />
<trace name="X24_DXIN_SIGNAL" from=".U_SOC > .DXIN" to="X1.pin1"
maxLength="10mm" maxViaCount={0} routingPhaseIndex={-150.2} />
<trace name="X24_DXIN_LOAD" from="X1.pin1" to="C_X24_IN.pin1"
maxLength="4mm" maxViaCount={0} routingPhaseIndex={-150.1} />
<trace from="C_X24_OUT.pin2" to="net.GND" maxLength="15mm" routingPhaseIndex={-105} />
<trace name="X24_INPUT_GROUND" from="C_X24_IN.pin2" to="net.GND"
maxLength="15mm" routingPhaseIndex={-104} />
<trace from="X1.pin2" to="net.GND" maxLength="15mm" routingPhaseIndex={-103} />
<trace from="X1.pin4" to="net.GND" maxLength="15mm" routingPhaseIndex={-102} />
<bus name="X24_DXOUT_SIGNAL_TOP" connections={["X24_DXOUT_SIGNAL"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-150.4} />
<bus name="X24_DXOUT_LOAD_TOP" connections={["X24_DXOUT_LOAD"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-150.3} />
<bus name="X24_DXIN_SIGNAL_TOP" connections={["X24_DXIN_SIGNAL"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-150.2} />
<bus name="X24_DXIN_LOAD_TOP" connections={["X24_DXIN_LOAD"]} pcbAllowedLayers={["top"]} routingPhaseIndex={-150.1} />
<TLV803SDBZR {...cleanImportedSilk} name="U_RESET" pcbX={14.0} pcbY={-14.5} pcbRotation={90} schSectionName={SECTION} />
<R name="R_RESET_PULLUP" resistance={part.r10k.value} mpn={part.r10k.mpn} lcsc={part.r10k.lcsc} x={9.0} y={-14.5} rotation={90} sectionName={SECTION} />
<C name="C_RESET_FILTER" capacitance={part.c100n.value} mpn={part.c100n.mpn} lcsc={part.c100n.lcsc} x={10.5} y={-14.5} rotation={90} sectionName={SECTION} />
<R name="R_RESET_ISO" resistance={part.r100.value} mpn={part.r100.mpn} lcsc={part.r100.lcsc} x={9.0} y={-13.0} rotation={90} sectionName={SECTION} />
<TS342A2P_WZ {...cleanImportedSilk} name="SW_RESET" pcbX={8.0} pcbY={-19.0} schSectionName={SECTION} />
<trace name="RESET_SUPERVISOR_POWER" from="U_RESET.VDD" to="net.VDD_3V3" maxLength="30mm" routingPhaseIndex={-144.3} />
<trace from="U_RESET.GND" to="net.GND" maxLength="20mm" routingPhaseIndex={-101} />
<trace name="RESET_PULLUP_POWER" from="R_RESET_PULLUP.pin1" to="net.VDD18_SOC" maxLength="20mm" routingPhaseIndex={-145.1} />
<trace from="C_RESET_FILTER.pin2" to="net.GND" maxLength="20mm" routingPhaseIndex={-100} />
<trace from="SW_RESET.pin2" to="net.GND" maxLength="25mm" routingPhaseIndex={-99} />
<trace name="RESET_SUPERVISOR_TO_FILTER" from="U_RESET.RESET" to="C_RESET_FILTER.pin1"
maxLength="8mm" maxViaCount={0} routingPhaseIndex={-149.89} />
<trace name="RESET_FILTER_TO_PULLUP" from="C_RESET_FILTER.pin1" to="R_RESET_PULLUP.pin2"
maxLength="5mm" maxViaCount={0} routingPhaseIndex={-149.88} />
<trace name="RESET_FILTER_TO_ISO" from="C_RESET_FILTER.pin1" to="R_RESET_ISO.pin1"
maxLength="5mm" maxViaCount={0} routingPhaseIndex={-149.87} />
<trace name="SOC_RESET_LOCAL" from=".U_SOC > .RESET" to="R_RESET_ISO.pin2"
maxLength="20mm" routingPhaseIndex={-149.9} />
<trace name="MANUAL_RESET_BRANCH" from="R_RESET_ISO.pin2" to="SW_RESET.pin1"
maxLength="20mm" routingPhaseIndex={-140.4} />
<R name="R_BOOT_SEL0" resistance={part.r10k.value} mpn={part.r10k.mpn} lcsc={part.r10k.lcsc} x={-0.5} y={-9.7} rotation={90} sectionName={SECTION} />
<R name="R_BOOT_SEL1" resistance={part.r10k.value} mpn={part.r10k.mpn} lcsc={part.r10k.lcsc} x={-1.9} y={-9.7} rotation={270} sectionName={SECTION} />
<TS342A2P_WZ {...cleanImportedSilk} name="SW_FEL" pcbX={-5.0} pcbY={-16.0} schSectionName={SECTION} />
<trace name="BOOT_SEL0_POWER" from="R_BOOT_SEL0.pin1" to="net.VDD_3V3" maxLength="30mm" routingPhaseIndex={-144.2} />
<trace name="BOOT_SEL0_TO_SOC" from="R_BOOT_SEL0.pin2" to=".U_SOC > .PC4"
width="0.10mm" maxLength="20mm" routingPhaseIndex={-149.48} />
<trace name="BOOT_SEL1_TO_SOC" from="R_BOOT_SEL1.pin1" to=".U_SOC > .PC5"
width="0.10mm" maxLength="20mm" routingPhaseIndex={-149.47} />
<trace from="R_BOOT_SEL1.pin2" to="net.GND" maxLength="20mm" routingPhaseIndex={-98} />
<trace name="FEL_BUTTON_TO_BOOT_SEL0" from="SW_FEL.pin1" to="R_BOOT_SEL0.pin2"
width="0.10mm" maxLength="25mm" routingPhaseIndex={-149.46} />
<trace from="SW_FEL.pin2" to="net.GND" maxLength="25mm" routingPhaseIndex={-97} />
<silkscreentext text="RESET" pcbX={19.0} pcbY={-19.0} fontSize="0.7mm" />
<silkscreentext text="USB FEL" pcbX={-5.0} pcbY={-18.4} fontSize="0.7mm" />
</subcircuit>
)
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