astra-abse/t113-s3

README.md

# T113-S3 fanout module

A reusable tscircuit escape-routing project for **Allwinner T113-S3, JLCPCB C5197687**. The component was imported with its exact JLCPCB/EasyEDA footprint. The source import is unchanged and protected by a SHA-256 regression test.

Install from [astra-abse/t113-s3](https://tscircuit.com/astra-abse/t113-s3):

```sh
tsci add astra-abse/t113-s3
```

```tsx
import { T113S3Module } from "@tsci/astra-abse.t113-s3"

export default () => (
  <board width={42} height={42} layers={4}>
    <schematicsheet name="Main" sheetWidth={432} sheetHeight={280}>
      <T113S3Module name="SOC" routingProfile="lcd_top_storage_right" />
    </schematicsheet>
  </board>
)
```

The deliverable is a **fanout module**, with real copper routes and native saved `<fanout pcbTracePaths={...}>` handoffs. It is not a complete powered or bootable T113-S3 board. Its scope is the requested escape routing; carrier power distribution, reset/clock circuitry, boot storage, and interface signal-integrity work remain separate.

## Run

Requires Node.js, npm, and Bun (verified with Bun 1.3.14).

```sh
bun install --frozen-lockfile
npm run verify
npm run dev
```

`npm run verify` type-checks, builds, runs regression and parent-board integration tests, runs all `@tscircuit/checks`, audits actual pad/trace/breakout geometry, and runs `tsci check shorts` in both Gerber and PCB modes on every layer. It fails on any error or warning in the built Circuit JSON. A separate analytic check uses intended source nets to verify copper clearance, including via segments and every ground-pour boundary/hole. A physical copper graph proves that all 30 capacitor power pads reach their assigned SoC pins, all 32 ground pads connect together, and every via touches copper on at least two layers. Negative tests deliberately remove a ground plane or power via and fill pour clearance holes.

The build uses `--disable-parts-engine` because the exact supplier footprint is already imported locally. This disables redundant supplier re-fetching; it does **not** disable DRC. No `--ignore-*` flags or diagnostic filtering are used.

Cloud publishing installs the committed lockfile, type-checks, and rebuilds the circuit. It reruns DRC, copper clearance, and physical connectivity audits, then requires the complete emitted circuit to match the locally verified artifact by SHA-256 (excluding filesystem metadata). This retains proof from both full-resolution short scans without repeating the slow bitmap scan for identical geometry. A changed cloud artifact fails publication verification.

Results are in `reports/verification.md`, `reports/verification.json`, and individual command logs. Generated PCB/schematic SVGs, PNGs, and Circuit JSON are in `dist/index/`.

### CLI bitmap renderer compatibility

CLI 0.1.2050 assumes an offscreen canvas has `getContext`, but its own bitmap canvas is a plain object. Pours combined with traces trigger a runtime exception. `scripts/patch-cli-bitmap.ts` applies a version-checked fix at install/verification time: use the renderer's existing direct-drawing fallback when `getContext` is absent. A bounding-box rejection also skips point-in-polygon work for points that cannot be inside a ring, preserving the same fill rule and 100 px/mm resolution.

The patch changes no net assignment, clearance rule, short decision, or diagnostic. `scripts/test-bitmap-renderer.ts` exercises a power pad isolated within a ground pour and deliberately removes its clearance hole to confirm the PCB-mode checker detects the injected short. Gerber-mode checks and the independent analytic polygon/trace/pad/via checker remain separate.

## API and reference compatibility

The API follows the reusable module pattern in [astra/f1c100s v0.9.2](https://tscircuit.com/astra/f1c100s#files), using `layoutProfile`. The requested `routingProfile` spelling and the earlier `busProfile` remain compatible aliases. This project implements one verified profile: `lcd_top_storage_right`.

```tsx
<T113S3Module
  name="SOC"
  layoutProfile="lcd_top_storage_right"
  pcbX={0}
  pcbY={0}
  pcbRotation={0}
  schX={0}
  schY={0}
  connections={{
    SDMMC0_D1: ".J_STORAGE > .pin1",
    SPI0_CLK: ".FLASH > .CLK",
    GND: "net.GND",
  }}
/>
```

`connections` accepts every imported pin label except `NC0`, plus the functional aliases in `src/terminals.ts`. It creates parent traces through core's breakout handoff. Explicit parent traces can use the imported chip labels:

```tsx
<trace from=".SOC .U1 > .PF0" to=".J_STORAGE > .pin1" />
```

The `connections` form is covered by a full parent-board routing test. Quarter-turn rotations (0, 90, 180, 270 degrees) and translated placements are tested against emitted copper. Exit directions are relative to the module. Use a unique selector-safe instance name and reserve its 36 × 36 mm routing area. Mount on the top PCB side of a four-layer board.

| Group | Signals | Exit |
| --- | --- | --- |
| RGB666 LCD | PD0–PD17 data; PD18 clock; PD19 DE; PD20 HSYNC; PD21 VSYNC | Top |
| SPI0 / SDC2 bank | PC2–PC7 | Right |
| SDMMC0 | PF0–PF5 | Right |
| Auxiliary | All other non-NC pins | Nearby edges; PD22 and LCD supplies also exit top |
| Ground | AGND pin 91 and EPAD pin 129 | Joined through the GND pours; EPAD exposes the GND edge exit |
| No-connect | Pin 106 (`NC0`) | Intentionally no copper route |

RGB666 aliases are `LCD_D2`–`LCD_D7`, `LCD_D10`–`LCD_D15`, `LCD_D18`–`LCD_D23`, plus `LCD_CLK`, `LCD_DE`, `LCD_HSYNC`, and `LCD_VSYNC`. SPI aliases include CLK, CS, MOSI, MISO, WP, and HOLD. SDMMC0 aliases include CLK, CMD, D0–D3. Firmware must select the appropriate pin mux. The PB-bank bits needed for full RGB888 are not part of the top-directed RGB666 bus.

All supply pins retain their individual imported names; the fanout does not merge power domains or generate power. AGND and EPAD share GND. Signal escapes are 0.10 mm wide; capacitor power traces are 0.12 mm. All 29 distinct vias are through vias with 0.45 mm copper diameter and 0.20 mm drills. Top carries the signal escapes. Bottom carries the capacitor bank, power routes, and a GND pour; inner1 carries a second GND plane. Inner2 is available for the carrier design. Both pours stay within the module's 34 × 34 mm square and follow its translated placement.

## Ground and decoupling

Select **Bottom** or **Inner1** in the PCB viewer to see the GND copper. The top-only view hides those planes. The three GND through vias connect the exposed-pad escape and AGND to both planes; the other 26 vias connect individual supply/reference pins to their capacitors. No via is floating.

![Bottom copper and GND pour](dist/index/ground-bottom.png)

Saved copper is loaded through core’s `pcbTracePaths` fanout API. The source audit rejects individual `pcbPath` declarations, manual vias, and trace hints. The generated paths include explicit wire endpoints at each via, so existing PCB viewers can display pad-to-via connections without changing the physical copper.

Thirty bottom-mounted 0402 capacitors provide local bypassing plus four bulk capacitors. All have a 6.3 V minimum rating. Their values follow the pin-compatible [100ask T113-Pro core schematic](https://dl.100ask.net/Hardware/MPU/100ask_t113-pro/100ASK_T113-Pro_Core-SCH_V1.2-OPEN.pdf). The T113 capacitor bank is bottom-mounted:

| Pins | Capacitors |
| --- | --- |
| Supply pins other than those below | 100 nF per pin |
| LDOA_OUT 28, LDO_IN 29, LDOB_OUT 30, AVCC 89 | 2.2 µF each |
| VRA2 90, VRA1 92 | 470 nF each |
| TVIN_VRP 110, TVIN_VRN 111 | 1 µF each |
| VDD_SYS0 46, VCC_DRAM0 48, VCC_IO 83, VDD_CORE0 116 | Additional 10 µF each |

The capacitors are generic BOM entries; only the SoC has a verified JLCPCB import. Select actual capacitors with adequate effective capacitance at the intended bias. Supply domains remain separate. This escape layout explicitly allows up to 25 mm capacitor routing; it has not been qualified for PDN impedance or high-frequency decoupling performance.

The schematic separates the SoC pin breakout from the labeled capacitor bank. Reference designators and ground branches are actual schematic elements, included in the checks.

## How the routes are built

The component follows [the reference’s saved fanout API](https://tscircuit.com/astra/f1c100s#files): physical components live inside one `<fanout pcbTracePaths={...}>`, and logical `<trace from to>` connections live outside it. Normal module builds load the stored paths; they do not run the fanout solver. Parent connections use the carrier autorouter.

`src/generated/lcd_top_storage_right.trace-paths.json` stores 188 port-to-exit paths in module-local millimetres. There are 127 perimeter exits and 61 internal joins (60 capacitor pads and AGND). Capacitor power paths share the matching supply escape. Shared physical vias are deduplicated by net and position before DRC, following the reference’s shared-via handling. The final routing phase checks coincident signal exits; GND exits join through the two included pours. The independent physical copper graph verifies those plane connections, with negative tests for missing copper.

The initial saved profile was converted from the verified v1.1.0 copper. Conversion preserves the imported footprint, capacitor placement, power routes, and ground planes; AGND now terminates at its ground-plane via. Individual trace paths and the old custom capacitor-routing generator have been removed. `scripts/normalize-saved-paths.ts` expands via endpoints for compatibility with existing canvas viewers without moving copper.

## Part provenance and verification scope

- [JLCPCB C5197687](https://jlcpcb.com/partdetail/T113-S3/C5197687); imported using `tsci import C5197687 --jlcpcb --use-exact-footprint`.
- [Allwinner T113-S3 datasheet v1.6](https://linux-sunxi.org/images/7/73/T113-s3_datasheet_v1.6.pdf), pin and mux tables 4-2/4-3, package drawing 7-2.
- `imports/provenance.json` records the exact import hash and command. `src/pins.ts` records its pad coordinates; every generated pad is checked against that data.

The imported exposed copper pad measures 5.5999888 mm square; the datasheet's package exposed-pad reference is 5.72 mm. The imported land pattern is preserved, with no claim that software DRC replaces land-pattern or fabrication review. Software checks cover connectivity and geometric routing rules, not power integrity, controlled impedance, matched USB/LVDS/DSI routing, or thermal performance.