astra-abse/t113-s3

reports/tests.log

bun test v1.3.14 (0d9b296a)

tests/fanout.test.tsx:
(pass) all imported pads escape to the declared boundary with clean DRC [570.54ms]
(pass) module translation and 0 degree rotation preserve the fanout [6732.90ms]
(pass) module translation and 90 degree rotation preserve the fanout [6708.97ms]
(pass) module translation and 180 degree rotation preserve the fanout [6660.88ms]
(pass) module translation and 270 degree rotation preserve the fanout [6710.42ms]
(pass) removing an escape is detected, rather than a vacuous clean DRC [203.94ms]
(pass) an injected bridge to a neighboring net is detected [224.88ms]
(pass) a stale breakout marker cannot hide an incomplete copper endpoint [7.18ms]
(pass) source-based copper audit catches a bridge ending exactly on another net's pad [511.54ms]
(pass) unsupported profiles fail explicitly [0.20ms]
(pass) the JLCPCB import is unchanged from its recorded provenance [10.44ms]
(pass) removing the bottom ground plane disconnects the capacitor returns [23.82ms]
(pass) a missing power via breaks the physical capacitor connection [45.86ms]
(pass) a ground pour without its clearance holes is detected as a short [112.51ms]

tests/handoff.test.tsx:
(pass) a parent trace connects through the exported storage breakout [7017.28ms]

 15 pass
 0 fail
 34 expect() calls
Ran 15 tests across 2 files. [42.68s]