astra/f1c100s
The code defines the physical pin layout, labels, and footprint for the F1C100S system-on-chip (SoC) component used in electronic devices.
- Version
- 0.9.2
- License
- unset
- Stars
- 0
src/generated/lcd_right_storage_left.metrics.json
PCB
Schematic
{
"profile": "lcd_right_storage_left",
"inputHash": "bb4e4b60fa3e75009ea6d283bfb811b01a884fbf11bb9da7f485ebcf902510ad",
"moduleSizeMm": 28,
"rules": {
"traceWidth": 0.12,
"clearance": 0.1,
"viaDiameter": 0.45,
"viaDrill": 0.2,
"layers": 4
},
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 902,
"vias": 196,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1365.822,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057,
"drcErrors": 0,
"optimization": {
"before": {
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 2942,
"vias": 265,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1473.276,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057
},
"after": {
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 902,
"vias": 196,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1365.822,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057
}
}
}