astra/f1c100s
The code defines the physical pin layout, labels, and footprint for the F1C100S system-on-chip (SoC) component used in electronic devices.
- Version
- 0.9.2
- License
- unset
- Stars
- 0
src/generated/lcd_top_storage_right.metrics.json
PCB
Schematic
{
"profile": "lcd_top_storage_right",
"inputHash": "de87b89ea205090085b2b1f814003156be9b137f54e9503cc3d3fd8cefa58c2e",
"moduleSizeMm": 28,
"rules": {
"traceWidth": 0.12,
"clearance": 0.1,
"viaDiameter": 0.45,
"viaDrill": 0.2,
"layers": 4
},
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 1154,
"vias": 239,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1598.188,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057,
"drcErrors": 0,
"optimization": {
"before": {
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 3569,
"vias": 301,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1683.303,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057
},
"after": {
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 1154,
"vias": 239,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1598.188,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057
}
}
}