seveibar/adm6-breakout

This code defines PCB designs featuring a 60-pin fanout or direct routing layout with multiple signal and power layers, test pads, and component footprints for a high-density electronic breakout board.

Version
1.0.2
License
unset
Stars
0

historical-full-integration.tsx

import { Fragment } from "react"
import { ADM6_60_03_5_L_4_0_A_TR } from "./imports/ADM6_60_03_5_L_4_0_A_TR"
import { ABM8_272_T3 } from "./imports/ABM8_272_T3"
import { RP2040 } from "./imports/RP2040"
import { W25Q16JVSSIQ } from "./imports/W25Q16JVSSIQ"

const CONTACTS_PER_ROW = 60
const BREAKOUT_PITCH_MM = 1.27
const SIGNAL_FANOUT_LAYERS = [
  "top",
  "bottom",
  "inner1",
  "inner2",
  "inner3",
  "inner4",
] as const

const padName = (row: string, position: number) =>
  `${row}${String(position).padStart(2, "0")}`

const railPinLabels = (row: string) =>
  Object.fromEntries(
    Array.from({ length: CONTACTS_PER_ROW }, (_, index) => [
      `pin${index + 1}`,
      [padName(row, index + 1)],
    ]),
  )

const FanoutEdgeRow = ({
  name,
  row,
  pcbY,
}: {
  name: string
  row: "A" | "B" | "C" | "D"
  pcbY: number
}) => (
  <chip
    name={name}
    displayName={`ADM6 row ${row} fanout edge`}
    noSchematicRepresentation
    pcbX={0}
    pcbY={pcbY}
    pinLabels={railPinLabels(row)}
    footprint={
      <footprint name={`ADM6_ROW_${row}_FANOUT_EDGE`}>
        {Array.from({ length: CONTACTS_PER_ROW }, (_, index) => (
          <Fragment key={`${row}-edge-${index + 1}`}>
            <smtpad
              pcbX={((CONTACTS_PER_ROW - 1) / 2 - index) * BREAKOUT_PITCH_MM}
              pcbY={0}
              width="0.8mm"
              height="0.8mm"
              shape="rect"
              layer="top"
              portHints={[`pin${index + 1}`]}
            />
          </Fragment>
        ))}
      </footprint>
    }
  />
)

const gpioMappings = [
  ...Array.from({ length: 16 }, (_, index) => ({
    gpio: `GPIO${index}`,
    rail: "EA",
    contact: padName("A", index + 1),
  })),
  ...Array.from({ length: 10 }, (_, index) => ({
    gpio: `GPIO${index + 16}`,
    rail: "EB",
    contact: padName("B", index + 1),
  })),
  ...Array.from({ length: 4 }, (_, index) => ({
    gpio: `GPIO${index + 26}_ADC${index}`,
    rail: "EB",
    contact: padName("B", index + 11),
  })),
] as const

const adm6Rows = [
  { row: "A", edge: "EA", edgeY: 9.25 },
  { row: "B", edge: "EB", edgeY: 7 },
  { row: "C", edge: "EC", edgeY: -7 },
  { row: "D", edge: "ED", edgeY: -9.25 },
] as const

const rp2040PowerPins = [
  "IOVDD1",
  "IOVDD2",
  "IOVDD3",
  "IOVDD4",
  "IOVDD5",
  "IOVDD6",
  "ADC_AVDD",
  "USB_VDD",
  "VREG_IN",
] as const

const decouplers = [
  { name: "C_IO1", pin: "IOVDD1", x: -13.5, y: 6.5 },
  { name: "C_IO2", pin: "IOVDD2", x: -10.5, y: 6.5 },
  { name: "C_IO3", pin: "IOVDD3", x: -7.5, y: 6.5 },
  { name: "C_IO4", pin: "IOVDD4", x: -4.5, y: 6.5 },
  { name: "C_IO5", pin: "IOVDD5", x: -1.5, y: 6.5 },
  { name: "C_IO6", pin: "IOVDD6", x: 1.5, y: 6.5 },
  { name: "C_ADC", pin: "ADC_AVDD", x: 4.5, y: 6.5 },
  { name: "C_USB", pin: "USB_VDD", x: 7.5, y: 6.5 },
] as const

export const ADM6Rp2040Board = ({
  routingDisabled = false,
}: {
  routingDisabled?: boolean
}) => (
  <board
    title="ADM6-60 RP2040 autorouter stress breakout"
    width="84mm"
    height="80mm"
    borderRadius="2mm"
    thickness="1.6mm"
    layers={8}
    allowBlindAndBuriedVias
    solderMaskColor="green"
    silkscreenColor="white"
    schematicDisabled
    routingDisabled={routingDisabled}
    autorouter="auto-local"
    autorouterEffortLevel="1x"
    minTraceWidth="0.1mm"
    defaultTraceWidth="0.1mm"
    minTraceToPadEdgeClearance="0.08mm"
    minPadEdgeToPadEdgeClearance="0.08mm"
    minViaEdgeToPadEdgeClearance="0.08mm"
    minViaHoleEdgeToViaHoleEdgeClearance="0.1mm"
    minViaHoleDiameter="0.2mm"
    minViaPadDiameter="0.45mm"
  >
    <copperpour
      name="GND_PLANE"
      connectsTo="net.GND"
      layer="inner5"
      clearance="0.12mm"
      boardEdgeMargin="0.5mm"
    />
    <copperpour
      name="V3V3_PLANE"
      connectsTo="net.V3V3"
      layer="inner6"
      clearance="0.12mm"
      boardEdgeMargin="0.5mm"
    />

    <fanout
      name="ADM6_FANOUT"
      pcbX={0}
      pcbY={-10}
      width="80mm"
      height="20mm"
      autorouter="fanout"
      fanoutRoutingLayers={[...SIGNAL_FANOUT_LAYERS]}
      busFanoutDirections={{
        ADM6_A: "top_center",
        ADM6_B: "top_center",
        ADM6_C: "bottom_center",
        ADM6_D: "bottom_center",
      }}
    >
      <ADM6_60_03_5_L_4_0_A_TR name="J1" pcbX={0} pcbY={0} />

      {adm6Rows.map(({ row, edge, edgeY }) => (
        <FanoutEdgeRow key={row} name={edge} row={row} pcbY={edgeY} />
      ))}

      {adm6Rows.map(({ row }) => (
        <Fragment key={`bus-${row}`}>
          <bus
            name={`ADM6_${row}`}
            connections={Array.from(
              { length: CONTACTS_PER_ROW },
              (_, index) =>
                `ADM6_${row}_${String(index + 1).padStart(2, "0")}`,
            )}
          />
        </Fragment>
      ))}

      {adm6Rows.flatMap(({ row, edge }) =>
        Array.from({ length: CONTACTS_PER_ROW }, (_, index) => {
          const contact = padName(row, index + 1)
          return (
            <Fragment key={`${row}-${contact}`}>
              <trace
                name={`ADM6_${row}_${String(index + 1).padStart(2, "0")}`}
                from={`.J1 > .${contact}`}
                to={`.${edge} > .${contact}`}
              />
            </Fragment>
          )
        }),
      )}
    </fanout>

    <fanout
      name="RP2040_FANOUT"
      pcbX={0}
      pcbY={24}
      width="44mm"
      height="23mm"
      autorouter="fanout"
      fanoutRoutingLayers={["top", "bottom", "inner1", "inner2"]}
      fanoutPourNetMap={{ inner5: "GND", inner6: "V3V3" }}
    >
      <RP2040 name="U1" pcbX={0} pcbY={0} />
      <W25Q16JVSSIQ name="U2" pcbX={-11.5} pcbY={0} pcbRotation={90} />
      <ABM8_272_T3 name="X1" pcbX={10.5} pcbY={0} />

      <trace name="FLASH_CS" from=".U1 > .QSPI_SS" to=".U2 > .CS_N" />
      <trace name="FLASH_CLK" from=".U1 > .QSPI_SCLK" to=".U2 > .CLK" />
      <trace name="FLASH_IO0" from=".U1 > .QSPI_SD0" to=".U2 > .IO0" />
      <trace name="FLASH_IO1" from=".U1 > .QSPI_SD1" to=".U2 > .IO1" />
      <trace name="FLASH_IO2" from=".U1 > .QSPI_SD2" to=".U2 > .IO2" />
      <trace name="FLASH_IO3" from=".U1 > .QSPI_SD3" to=".U2 > .IO3" />
      <trace from=".U2 > .VCC" to="net.V3V3" />
      <trace from=".U2 > .GND" to="net.GND" />

      <trace name="XIN_U1" from=".U1 > .XIN" to="net.XIN" />
      <trace name="XIN_X1" from=".X1 > .pin1" to="net.XIN" />
      <resistor
        name="R_XOUT"
        resistance="1k"
        footprint="0402"
        pcbX={7}
        pcbY={-3}
      />
      <trace from=".X1 > .pin3" to=".R_XOUT > .pin1" />
      <trace name="XOUT_R" from=".R_XOUT > .pin2" to="net.XOUT" />
      <trace name="XOUT_U1" from=".U1 > .XOUT" to="net.XOUT" />
      <trace from=".X1 > .GND1" to="net.GND" />
      <trace from=".X1 > .GND2" to="net.GND" />
      <capacitor
        name="C_XIN"
        capacitance="15pF"
        footprint="0402"
        pcbX={8}
        pcbY={3.5}
      />
      <capacitor
        name="C_XOUT"
        capacitance="15pF"
        footprint="0402"
        pcbX={12.5}
        pcbY={3.5}
      />
      <trace name="XIN_C" from=".C_XIN > .pin1" to="net.XIN" />
      <trace from=".C_XIN > .pin2" to="net.GND" />
      <trace name="XOUT_C" from=".C_XOUT > .pin1" to="net.XOUT" />
      <trace from=".C_XOUT > .pin2" to="net.GND" />

      {rp2040PowerPins.map((pin) => (
        <Fragment key={pin}>
          <trace from={`.U1 > .${pin}`} to="net.V3V3" />
        </Fragment>
      ))}
      <trace from=".U1 > .DVDD1" to="net.V1V1" />
      <trace from=".U1 > .DVDD2" to="net.V1V1" />
      <trace from=".U1 > .VREG_VOUT" to="net.V1V1" />
      <trace from=".U1 > .GND" to="net.GND" />
      <trace from=".U1 > .TESTEN" to="net.GND" />

      {decouplers.map(({ name, pin, x, y }) => (
        <Fragment key={name}>
          <capacitor
            name={name}
            capacitance="100nF"
            footprint="0402"
            pcbX={x}
            pcbY={y}
          />
          <trace name={`${name}_${pin}`} from={`.${name} > .pin1`} to="net.V3V3" />
          <trace from={`.${name} > .pin2`} to="net.GND" />
        </Fragment>
      ))}
      <capacitor
        name="C_VREG_IN"
        capacitance="1uF"
        footprint="0603"
        pcbX={11}
        pcbY={-5.5}
      />
      <trace name="VREG_IN_BULK" from=".C_VREG_IN > .pin1" to="net.V3V3" />
      <trace from=".C_VREG_IN > .pin2" to="net.GND" />
      <capacitor
        name="C_VREG_OUT"
        capacitance="1uF"
        footprint="0603"
        pcbX={5}
        pcbY={-5.5}
      />
      <trace from=".C_VREG_OUT > .pin1" to="net.V1V1" />
      <trace from=".C_VREG_OUT > .pin2" to="net.GND" />
      <capacitor
        name="C_FLASH"
        capacitance="100nF"
        footprint="0402"
        pcbX={-15}
        pcbY={4}
      />
      <trace name="FLASH_DECOUPLE" from=".C_FLASH > .pin1" to="net.V3V3" />
      <trace from=".C_FLASH > .pin2" to="net.GND" />

      <resistor
        name="R_RUN"
        resistance="10k"
        footprint="0402"
        pcbX={16}
        pcbY={-6}
      />
      <trace from=".R_RUN > .pin1" to=".U1 > .RUN" />
      <trace from=".R_RUN > .pin2" to="net.V3V3" />

      <pinheader
        name="J_SWD"
        pinCount={4}
        pitch="2.54mm"
        footprint="pinrow4"
        pcbX={18}
        pcbY={6}
        pcbRotation={90}
        pinLabels={["SWD", "SWCLK", "RUN", "GND"]}
      />
      <trace from=".J_SWD > .SWD" to=".U1 > .SWD" />
      <trace from=".J_SWD > .SWCLK" to=".U1 > .SWCLK" />
      <trace from=".J_SWD > .RUN" to=".U1 > .RUN" />
      <trace from=".J_SWD > .GND" to="net.GND" />

      <pinheader
        name="J_PWR"
        pinCount={2}
        pitch="2.54mm"
        footprint="pinrow2"
        pcbX={-19}
        pcbY={-7}
        pcbRotation={90}
        pinLabels={["3V3", "GND"]}
      />
      <trace from=".J_PWR > .3V3" to="net.V3V3" />
      <trace from=".J_PWR > .GND" to="net.GND" />
    </fanout>

    {gpioMappings.map(({ gpio, rail, contact }) => (
      <Fragment key={gpio}>
        <trace
          name={`MCU_${gpio}`}
          from={`.U1 > .${gpio}`}
          to={`.${rail} > .${contact}`}
        />
      </Fragment>
    ))}

    <trace from=".EA > .A57" to="net.V3V3" />
    <trace from=".EA > .A58" to="net.GND" />
    <trace from=".EA > .A59" to=".U1 > .SWD" />
    <trace from=".EA > .A60" to=".U1 > .SWCLK" />
    <trace from=".EB > .B57" to=".U1 > .RUN" />
    <trace from=".EB > .B58" to=".U1 > .USB_DM" />
    <trace from=".EB > .B59" to=".U1 > .USB_DP" />
    <trace from=".EB > .B60" to="net.GND" />

    <silkscreentext
      text="ADM6-60 / RP2040 AUTOROUTE STRESS BREAKOUT"
      fontSize="1.2mm"
      pcbX={0}
      pcbY={38}
    />
    <silkscreentext text="A60" fontSize="0.8mm" pcbX={-39.5} pcbY={-0.75} />
    <silkscreentext text="A01" fontSize="0.8mm" pcbX={39.5} pcbY={-0.75} />
    <silkscreentext text="D60" fontSize="0.8mm" pcbX={-39.5} pcbY={-19.25} />
    <silkscreentext text="D01" fontSize="0.8mm" pcbX={39.5} pcbY={-19.25} />
    <silkscreentext text="3V3 IN" fontSize="0.8mm" pcbX={-18} pcbY={34} />
    <silkscreentext text="SWD" fontSize="0.8mm" pcbX={18} pcbY={34} />

    <hole name="H1" diameter="3.2mm" pcbX={-39} pcbY={36.5} />
    <hole name="H2" diameter="3.2mm" pcbX={39} pcbY={36.5} />
    <hole name="H3" diameter="3.2mm" pcbX={-39} pcbY={-36.5} />
    <hole name="H4" diameter="3.2mm" pcbX={39} pcbY={-36.5} />
  </board>
)

export default ADM6Rp2040Board