tscircuit/autorouting-dataset-01
This code manages the hardware and electronic components for circuit design and PCB layout, defining components like resistors, capacitors, transistors, connectors, and footprints, and providing tools for component placement, PCB topology, and electrical connections.
- Version
- 1.0.102
- License
- unset
- Stars
- 4
lib/dataset/circuit001.simple-route.json
{
"bounds": {
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"maxX": 6,
"minY": -15,
"maxY": 15
},
"obstacles": [
{
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"source_port_4",
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"pcb_port_4"
]
},
{
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]
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{
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]
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{
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{
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{
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{
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{
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]
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{
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"source_trace_7",
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"source_trace_1",
"source_port_1",
"source_trace_0",
"source_port_0",
"source_net_0",
"pcb_smtpad_8",
"pcb_port_0",
"pcb_smtpad_9",
"pcb_port_1",
"pcb_smtpad_17",
"pcb_port_17"
]
},
{
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"source_port_0",
"source_net_0",
"pcb_smtpad_8",
"pcb_port_0",
"pcb_smtpad_9",
"pcb_port_1",
"pcb_smtpad_17",
"pcb_port_17"
]
},
{
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"source_trace_5",
"source_port_19",
"source_trace_3",
"source_port_3",
"source_trace_2",
"source_port_2",
"source_net_1",
"pcb_smtpad_10",
"pcb_port_2",
"pcb_smtpad_11",
"pcb_port_3",
"pcb_plated_hole_5",
"pcb_port_19"
]
},
{
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"source_port_3",
"source_trace_2",
"source_port_2",
"source_net_1",
"pcb_smtpad_10",
"pcb_port_2",
"pcb_smtpad_11",
"pcb_port_3",
"pcb_plated_hole_5",
"pcb_port_19"
]
},
{
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]
},
{
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]
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{
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"source_port_15",
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"pcb_port_15"
]
},
{
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]
},
{
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"layers": [
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],
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"connectedTo": [
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"source_trace_6",
"source_port_23",
"source_port_16",
"pcb_smtpad_16",
"pcb_port_16",
"pcb_smtpad_19",
"pcb_port_23"
]
},
{
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},
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"source_trace_7",
"source_port_17",
"source_trace_1",
"source_port_1",
"source_trace_0",
"source_port_0",
"source_net_0",
"pcb_smtpad_8",
"pcb_port_0",
"pcb_smtpad_9",
"pcb_port_1",
"pcb_smtpad_17",
"pcb_port_17"
]
},
{
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"pcb_plated_hole_4",
"pcb_port_18",
"pcb_smtpad_18",
"pcb_port_22"
]
},
{
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],
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"source_trace_6",
"source_port_23",
"source_port_16",
"pcb_smtpad_16",
"pcb_port_16",
"pcb_smtpad_19",
"pcb_port_23"
]
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{
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{
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{
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{
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]
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{
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],
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"connectedTo": [
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"connectivity_net10",
"source_trace_4",
"source_port_18",
"source_port_22",
"pcb_plated_hole_4",
"pcb_port_18",
"pcb_smtpad_18",
"pcb_port_22"
]
},
{
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],
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"connectedTo": [
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"connectivity_net13",
"source_trace_5",
"source_port_19",
"source_trace_3",
"source_port_3",
"source_trace_2",
"source_port_2",
"source_net_1",
"pcb_smtpad_10",
"pcb_port_2",
"pcb_smtpad_11",
"pcb_port_3",
"pcb_plated_hole_5",
"pcb_port_19"
]
},
{
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"inner2",
"bottom"
],
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"connectivity_net80",
"source_port_20",
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"pcb_port_20"
]
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{
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"connectedTo": [
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"pcb_port_21"
]
},
{
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],
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"connectedTo": []
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{
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}
],
"connections": [
{
"name": "source_trace_4",
"source_trace_id": "source_trace_4",
"pointsToConnect": [
{
"x": -3.25,
"y": -2.25,
"layer": "top",
"pointId": "pcb_port_18",
"pcb_port_id": "pcb_port_18"
},
{
"x": -3.825,
"y": 7,
"layer": "top",
"pointId": "pcb_port_22",
"pcb_port_id": "pcb_port_22"
}
]
},
{
"name": "source_trace_6",
"source_trace_id": "source_trace_6",
"pointsToConnect": [
{
"x": -2.175,
"y": 7,
"layer": "top",
"pointId": "pcb_port_23",
"pcb_port_id": "pcb_port_23"
},
{
"x": 2.175,
"y": 12,
"layer": "top",
"pointId": "pcb_port_16",
"pcb_port_id": "pcb_port_16"
}
]
},
{
"name": "source_net_0",
"pointsToConnect": [
{
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"y": -8.05091295000011,
"layer": "top",
"pointId": "pcb_port_0",
"pcb_port_id": "pcb_port_0"
},
{
"x": -3.0500319999999874,
"y": -8.05091295000011,
"layer": "top",
"pointId": "pcb_port_1",
"pcb_port_id": "pcb_port_1"
},
{
"x": 3.825,
"y": 12,
"layer": "top",
"pointId": "pcb_port_17",
"pcb_port_id": "pcb_port_17"
}
]
},
{
"name": "source_net_1",
"pointsToConnect": [
{
"x": -2.5499059999999645,
"y": -8.05091295000011,
"layer": "top",
"pointId": "pcb_port_2",
"pcb_port_id": "pcb_port_2"
},
{
"x": -2.249932000000058,
"y": -8.05091295000011,
"layer": "top",
"pointId": "pcb_port_3",
"pcb_port_id": "pcb_port_3"
},
{
"x": 3.25,
"y": -2.25,
"layer": "top",
"pointId": "pcb_port_19",
"pcb_port_id": "pcb_port_19"
}
]
}
],
"layerCount": 2,
"minTraceWidth": 0.15
}
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