0hmX/am3352

docs/ddr-a9-power-launch-improvement.md

# Verified A9 power-launch improvement

`dist/ddr-integrated-ten-power52` preserves the ten-host candidate, including its DQ12 transition, and qualifies **52 of 60** actual RAM pad-to-plane launches. `dist/ddr-integrated-nine-power52` preserves the earlier nine-host baseline independently. Neither parent directory is modified.

Both RAM A9 pads now reach an inner3 supply via over a straight 0.55 mm top-layer trace. Vias use 0.4572 mm copper and 0.254 mm drill. Each serves one RAM ball. Four unused bottom-layer ground tails (A8/B8 on each RAM) are removed after their existing vias; their pad connections and full inner1 plane contacts remain. Two new power-via antipads on each of inner1 and inner5 retain the previous plane boundaries and holes.

The combined ten-host result has zero physical errors or clearance violations, 0.1016 mm minimum clearance, valid maximum-45-degree route bends, zero invalid joined bends, and ten physically connected host nets. All existing and new plane contact witnesses pass 32/32 annulus samples. The actual source-pad audit independently measures the two new 0.55 mm launches and reports 52 connected/qualified pads. Eight remain unresolved: VSSQ_D1, VDDQ_B9, VSSQ_D9 and VDDQ_E9 on each RAM. This does not establish complete DDR timing, impedance, or PDN signoff.

`original-copper-replacements.json` records exact before/after objects and SHA-256 hashes for six traces and two planes. Every other element, including support components and host geometry, must remain exact. The generator first validates its parent against the frozen original and inherited power replacements, then validates the child as an explicit patch. The legacy support loader alone deliberately rejects this child: subsequent routing must retain and validate this replacement chain, rather than waive original preservation. Historical edge-breakout objects are retained for provenance; the six replaced traces retire their associated edge-handoff metadata.

Reproduce with:

```sh
bun scripts/improve-ddr-a9-power-launches.ts dist/ddr-integrated-ten dist/ddr-system/host-taps-54af3e346b5e dist/ddr-integrated-ten-power52
bun test tests/ddr-a9-power-launches.test.ts
```

The generator runs both full alias-free copper validation and the actual pad-to-plane audit before returning success. Report provenance pins the frozen capture, parent circuit, every declared replacement, child circuit and launch audit.

## B9 sharing improvement: 54/60

`dist/ddr-integrated-ten-power54` additionally connects B9 on each RAM to its new A9 supply via. Each top-layer route has one 45-degree bend and a 1.027917459 mm pad-to-via centerline. No via or plane changes are required. The source-pad audit confirms exactly two RAM balls per shared via, preserves all previous 52 qualified launches and now qualifies **54/60**. Six remain: VSSQ_D1, VSSQ_D9 and VDDQ_E9 on each RAM.

Full alias-free copper validation reports zero errors/violations, valid maximum-45-degree bends, zero invalid joined bends, all ten connected host nets and 0.1016 mm minimum clearance. Every existing plane contact still passes 32/32 annulus samples. The new manifest declares exactly two trace replacements, validated through the complete original baseline → power52 → power54 chain. Host routes, support components, vias and planes remain exact.

```sh
bun scripts/improve-ddr-b9-shared-power-launches.ts
bun test tests/ddr-b9-shared-power-launches.test.ts
```

## D9 ground improvement: 56/60

`dist/ddr-integrated-ten-power56` adds straight 0.55 mm D9 ground launches on both RAMs. Each uses a new 0.4572/0.254 mm through via contacting both ground planes, with 32/32 annulus samples. Two unused D7 power tails are trimmed only after their existing plane-connected vias, clearing the new ground barrels. The supply plane gains two antipads; both ground planes remain exact. Nearest existing via copper-edge spacing is 0.573434 mm.

The actual audit proves **56/60**, preserving all prior 54 qualified launches. All ten host nets remain connected. Full alias-free copper validation reports zero errors/violations, valid maximum-45-degree bends, zero invalid joined bends and 0.1016 mm minimum clearance. The recursive baseline → power52 → power54 → power56 manifest chain declares four trace changes and one plane change in this step. Four launches remain: VSSQ_D1 and VDDQ_E9 on each RAM. Their tested outward new-barrel locations conflict with retained inner2 signal copper; no remaining launch is claimed solved.

```sh
bun scripts/improve-ddr-d9-ground-launches.ts
bun test tests/ddr-d9-ground-launches.test.ts
```

## Integrated CPU supply junction correction

`dist/ddr-facing-progress-45` preserves all eleven routed hosts and 56 qualified RAM power launches while correcting the CPU K6/L6 supply branch. Exactly one original trace changes: `pcb_trace_3`, explicitly owned by `source_trace_3` / `FIXED_DROP_K6`. Its top-layer path is `(9.2,-0.4) → (9,-0.6) → (9,-1) → (9.2,-1.2) → (9.6,-1.6)` mm, widened from 0.08128 to 0.1016 mm. Actual K6 pad and same-source supply-via witnesses are retained in the manifest.

The original-width trial passed clearance and angles but failed the new-trace minimum-width rule. The widened final candidate passes without waiving that rule: zero physical errors/violations, 0.1016 mm minimum clearance, zero all-candidate junction violations and zero all-candidate angle violations. Plane geometry is unchanged and hashed; all plane contacts and all 56 RAM launches are rechecked. Parent candidate/report/host/input/power files and frozen capture are checked before and after verification. Every other circuit element is exact.

```sh
bun scripts/repair-ddr-cpu-supply-junction.ts
bun test tests/ddr-cpu-supply-junction.test.ts
```