This code defines the hardware connections and routing logic for a DDR memory interface, specifying physical signal mappings between the system-on-chip (SoC) and DDR memory components, including connections for data, address, clock, reset, and power/ground balls.
# Clean AM62L32 + LPDDR4 project
A fixed, standalone extraction of the AM62L/LPDDR4 progressive-fanout fixture.
There are no render options, test assertions, snapshot helpers, or imports from
the core test tree.
- U1: TI AM62L32, 373-ball FCCSP
- U2: Micron MT53E1G16D1ZW LPDDR4
- 31 DDR signals in seven buses
- GND on inner1
- VDD_LPDDR4 on inner2
- SOC_DVDD1V8 on inner3
- preferred signal layers: top, inner4, inner5, inner6, and bottom
Physical routing is intentionally disabled in the default build. The current
fanout solver can escape only 22 of the 33 required SoC breakout connections;
leaving routing disabled keeps this project honest and buildable while retaining
the complete checked electrical design.
Run `bun install`, then `bun run build`.