0hmX/am62l-lpddr4-clean

This code defines the hardware connections and routing logic for a DDR memory interface, specifying physical signal mappings between the system-on-chip (SoC) and DDR memory components, including connections for data, address, clock, reset, and power/ground balls.

Version: 1.0.0
License: unset
Stars: 0

ddr-connections.ts

export type DdrBusName =
  | "DDR_BYTE0"
  | "DDR_BYTE1"
  | "DDR_ADDR_CTRL"
  | "DDR_CLOCK"
  | "DDR_DQS0"
  | "DDR_DQS1"
  | "DDR_RESET"

export interface DdrConnection {
  bus: DdrBusName
  memorySignal: string
  socSignal: string
  trace: string
}

const byteConnections = Array.from({ length: 16 }, (_, bit) => ({
  bus: bit < 8 ? ("DDR_BYTE0" as const) : ("DDR_BYTE1" as const),
  memorySignal: `DQ${bit}`,
  socSignal: `DDR0_DQ${bit}`,
  trace: `DQ${bit}`,
}))

const fixedConnections = [
  ["DDR_ADDR_CTRL", "CA0", "DDR0_A0"],
  ["DDR_ADDR_CTRL", "CA1", "DDR0_A1"],
  ["DDR_ADDR_CTRL", "CA2", "DDR0_A2"],
  ["DDR_ADDR_CTRL", "CA3", "DDR0_A3"],
  ["DDR_ADDR_CTRL", "CA4", "DDR0_A4"],
  ["DDR_ADDR_CTRL", "CA5", "DDR0_A5"],
  ["DDR_ADDR_CTRL", "CS", "DDR0_CS0_n"],
  ["DDR_ADDR_CTRL", "CKE", "DDR0_CKE0"],
  ["DDR_CLOCK", "CK_t", "DDR0_CK0"],
  ["DDR_CLOCK", "CK_c", "DDR0_CK0_n"],
  ["DDR_DQS0", "DQS0_t", "DDR0_DQS0"],
  ["DDR_DQS0", "DQS0_c", "DDR0_DQS0_n"],
  ["DDR_DQS1", "DQS1_t", "DDR0_DQS1"],
  ["DDR_DQS1", "DQS1_c", "DDR0_DQS1_n"],
  ["DDR_RESET", "RESET_n", "DDR0_RESET0_n"],
] as const

export const DDR_CONNECTIONS: readonly DdrConnection[] = [
  ...byteConnections,
  ...fixedConnections.map(([bus, memorySignal, socSignal]) => ({
    bus,
    memorySignal,
    socSignal,
    trace: memorySignal,
  })),
]

export const tracesFor = (bus: DdrBusName) =>
  DDR_CONNECTIONS.filter((connection) => connection.bus === bus).map(
    (connection) => connection.trace,
  )