0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

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1.0.5
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unset
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docs/ddr-d9-facing-host.md

# DDR_D9 right-facing escape and host

The latest integration is `dist/ddr-fifteen-reference-repaired`: DM1 now matches the 27 mm DQS1 mean, while D9 still needs matching. Thirty-five interface nets remain unconnected. The DQS0 projected reference gap is repaired on all three planes in that current integration; signal geometry remains unchanged.

The D9-specific accepted result is `dist/ddr-fifteen-d9-connected`, derived from
`dist/ddr-fourteen-shorter-strobes`. Candidate object SHA256:
`128f18387f9002f87c0f45b4215baa2c4df1df89e9e995de075da8297970019f`.

DDR_D9 is RAM byte 1 DQ1, RAM ball C7, CPU ball K1. The explicit source chain is
RAM saved `source_trace_639` to global `source_trace_687`. Its retained package
via is at world (−13.999946, 2.900108). The 72-path byte-1 cache changes C7 in
addition to the parent's B7 mask change; the other 70 paths remain unchanged.

| Contract | Value |
| --- | --- |
| World exit side and direction | Right, 0° |
| Local exit side and direction | Left, 180° (RAM rotated 180°) |
| World exit | (−6.040077, 3.3), inner6 |
| Local exit | (−5.959923, 3.2), inner6 |
| Package launch | top → inner6, retained full ten-layer barrel |
| Host transition | (−5.6, 2.9), top ↔ inner6, full ten-layer barrel |
| Trace width | 0.12 mm |
| Added padding, left/right/top/bottom | 0 / 0 / 0 / 0 mm |

The source-owned full planar length is **21.723228445028 mm**, below byte 1's
27.3001 mm nominal limit. It is not yet matched to the current 27 mm DQS1 mean.
The right-facing escape's optimistic escape-plus-host floor is 21.629547720563 mm.

The final board has 15 connected hosts, 30 accepted endpoint contacts, no physical
clearance violations, and passing self-contact, planar-angle, joined-bend and
terminal checks. All previous 14 hosts are exact. The new conventional host barrel
has an explicit antipad on each reference plane. Fresh power auditing retains
56 qualified launches out of 60; the four unresolved launches and the inherited
DQS0 reference-projection gap remain recorded. This is not full DDR timing or SI
qualification.

The artifact contains exact before/after replacement and addition witnesses,
both RAM caches and side/direction/layer contracts, current routing input,
source provenance, power/reference diagnostics and current byte budgets. No
external RAM source or canonical board was edited.