0hmX/am3352

docs/ddr-memory-compatibility.md

# Micron memory interface contract

The supplied package is **MT41K512M8DA-107 IT:P**, a 4-Gbit ×8 DDR3L device. Two packages form the AM3352 ×16 rank. The part is capable of DDR3 1.5-V operation; its 1866-MT/s speed grade does not establish the AM3352 interface speed. See [Micron 4Gb DDR3L Rev R](https://atta.szlcsc.com/upload/public/pdf/source/20241017/DD693FFA66FA4C721D9CFF3534518DFE.pdf), ball descriptions pp19–20 and 1.5-V operation section.

## Supplied cache and layer mapping

The external package was changing during this audit. Earlier documentation described four layers and matched long collectors while `bus-rules.ts` already specified six layers. At the inspected cache SHA-256 `cba82475b3dcd58156cdb6b5d76e8e379b93a051426dd93b480673ecbaa3d5a8`, `bus_grouped.trace-paths.json` has the new six-layer geometry:

| Source layer | Ten-layer host | Role |
|---|---|---|
| top | top | Package dogbones |
| inner1 | inner1 | Ground reference |
| inner2 | inner2 | DQ, DM, DQS |
| inner3 | inner4 | Address, bank, control, clock |
| inner4 | inner5 | Ground reference |
| bottom | bottom | Supply/reference escapes |

`DDR_MEMORY_SIX_LAYER_MAP` implements this mapping. Pass it explicitly to `adaptDdrMemoryPaths` or `DdrMemoryAdapter`; the default mapping preserves compatibility with the original four-layer caches. Never choose a mapping based only on the profile name. Inspect the actual cache layers and reject stale metadata. Copper widths remain those of the source unless the caller explicitly supplies `traceWidthMm`; the adapter does not establish impedance. Enlarged host vias need clearance verification against every pad and route.

The inspected boundary is X −5.959923 to +5.00505 mm and Y −5.25 to +5.425092 mm, anchored to the package center. Pass the actual source boundary to the adapter. Tests verify that an asymmetric boundary preserves pad and exit coordinates under all four orthogonal rotations.

## Placement consequences

The byte bus is split across both package edges: DQ0/2/4/6 and DQS leave west; DQ1/3/5/7 and DM leave east. Clock leaves east; address/control use both banks. Placing a RAM simply next to the CPU does not make every exit face the CPU. Far-side routes require clear corridors around the package and continuous reference planes. The grouped profile is preferable to mixed-layer compact profiles because each timing group has a consistent signal layer; its split sides remain a host-routing requirement.

## Required support wiring

`getDdrMemorySupportConnections(pins, targets)` enumerates every VDD, VDDQ, VSS and VSSQ ball separately, both references and ZQ. Combine its result with `getDdrMemoryConnections(cpu, byte)` to cover the 72 routed terminals. The helper deliberately requires explicit host targets. It does not place copper, capacitors, supply planes or a reference source.

Use a separate **240 Ω ±1% resistor from each RAM's ZQ to VSSQ** (Micron pp20 and67). ZQ is not a digital bus and must not connect directly to ground or another device's ZQ. VREFCA/VREFDQ require a quiet nominal half-VDDQ reference; it is not the VTT termination rail. Every supply ball needs physical power/ground continuity with suitable local decoupling and return paths. Capacitance, capacitor placement and PDN acceptance remain host-board design work; no unsupported decoupling network is implied by this wiring model.

B7 is DM with TDQS disabled; A7/TDQS# is intentionally omitted. Software initialization must agree with that mode. Clock/address termination, ODT, timing training and complete routed delay budgets are still required for a working interface. Local 45° bends and a rendered netlist alone do not prove these conditions.

## Measured integration gap and explicit correction

The inspected six-layer grouped cache passes the 45° bend audit and renders all 72 saved connections, 78 pads and 52 full-depth host vias. However, the independent copper check finds **69 geometric pair checks below the host's 0.1016-mm clearance rule**, with a minimum **0.1000 mm**. Several neighboring 0.12-mm tracks have 0.22-mm pitch. This satisfies the source's 0.10-mm rule but does not satisfy the stricter CPU integration rule. The enlarged via model includes every ten-layer barrel and all 78 original pads, including NC pads.

`bun scripts/check-ddr-integration.ts /path/to/memory-fanout` records source hashes, angles, the explicit width override and clearance violations. The four original compact caches pass at a measured 0.111246-mm minimum but retain mixed bus layers. A valid rendered adapter does not override this measured clearance mismatch. The source geometry itself remains unchanged and must not be reported as passing the stricter host rule.

The host adapter now permits an **explicit 0.1168-mm (4.6-mil) width** for the grouped cache. This is above the 0.1016-mm minimum and increases copper clearance without moving the centerlines or weakening the spacing rule. Use `adaptDdrMemoryPaths(paths, DDR_MEMORY_SIX_LAYER_MAP, 0.1168)` or `<DdrMemoryAdapter layerMap={DDR_MEMORY_SIX_LAYER_MAP} traceWidthMm={0.1168} ... />`. No override is applied implicitly.

The full ten-layer copper audit of this explicit adaptation resolves all 69 violations and measures a minimum **0.1019469134 mm**, with all 78 pads and full via barrels included. The integration scripts select and record this width for `bus_grouped`. Recompute controlled impedance against the actual stackup for this width; clearance acceptance does not establish impedance. Default/legacy adapters retain the source's 0.12-mm width.

## Separate external support-fixture audit — 2026-09-11

A later support experiment in the supplied RAM project is more complete than the original fanout-only integration. It is **not imported into the accepted CPU capture**. The source task was editing this experiment independently; its formerly reported process had ended. A fresh invocation of `capture-am3352-support.tsx` was therefore directed exclusively into this repository's `dist/ddr-support-external-audit/capture/`. No external source or output was modified. All inspected source hashes matched before and after that capture.

Frozen evidence:

| Artifact | SHA-256 |
|---|---|
| Captured `circuit.json` | `51115615c5fee2f91cd5ad7197e80c2f71ee1b6945bbd9ca054ea9bc8bdd2094` |
| External `capture-am3352-support.tsx` | `35a3adb69b58e03a57c186ce661afb8394daaf9e2621489ce91f511d5de00fd9` |
| External `am3352-support-routing.tsx` | `4975694ffc5524ac07f4cf99f057e26a718e74c1486da7e9179f7485dcd43a3e` |
| External `am3352-bypass-placement.json` | `89b5d2fefec293a0a3c9776d042b43c06347e04a6066b2f09676d0717772b2d6` |

`source-before.json` and `source-after.json` preserve the complete inspected file set. The support capture contains **35 added capacitors**: 26 local 100 nF bypass capacitors (13 per RAM), four 22 µF bulk capacitors and five VREF bypass capacitors. It also contains two 240 Ω ZQ resistors, a 49.9 Ω CPU VTP resistor, a 10 kΩ/10 kΩ VREF divider, and three host reference/power pours on inner1/inner5 GND and inner3 DDR_1V5. The four existing RAM reference regions remain, yielding seven copper pours. All 457 saved CPU/RAM routes are preserved.

The captured report establishes logical coverage of all 66 RAM support terminals and physical ball-to-plane contact for all 60 RAM supply/ground balls. Its annulus checks report 182/182 GND-via contacts on each ground plane and 85/85 contacts on the DDR supply plane. HS capacitor centers satisfy the 3.81 mm power-and-ground proximity check. The separate local support audit passes all 14 appended VREF/ZQ/VTP traces, with a measured minimum clearance of 0.111246 mm. That audit's stated scope is those routes and two CPU support vias; it is not a full acceptance of all new support geometry.

Important remaining failures are explicit in the frozen evidence:

- **All 38 originally missing outer supply/ground connection vias remain too far from their balls.** The fixture appends vias after the saved edge escapes instead of shortening those escapes. Measured paths are approximately 2.560–4.126 mm, exceeding 1.524 mm. Its `all60BallToViaLengthsWithinTiLimit` remains false even though plane connectivity is true. The separately developed early-drop candidates in this CPU worktree therefore remain relevant, but must be revalidated against any replacement support layout.
- **The user’s strict 45° rule fails twice** in actual captured copper: `pcb_trace_285`, the VREF divider bridge, contains two 90° turns. Zero emitted core errors does not override this independent angle audit.
- **The seven already verified host routes cannot be appended unchanged.** After remapping their electrical identities by actual source-port names, all seven retain geometric continuity, but the full physical checker reports **37 conflicts** against this support fixture. Twelve are contacts between new data-via barrels and the new global planes, requiring explicit antipads/repouring. The other 25 are actual trace/via or trace/trace clearance conflicts.

For example, `DROP_RAM0_VDDQ_C1` at (−4.840077, −10.099892) mm intersects the tuned DQS0 corridor, with signed clearance reaching −0.153403 mm. The CPU VREF/VTP support vias at (2.2, −0.4)/(2.2, 1.2) mm intersect DQS1, reaching −0.148600 mm. `seven-route-check.json` retains full shape descriptors; `seven-conflicts-summary.json` identifies the affected support elements. This result is an explicit rejection, not a new seven-net acceptance.

The external bank and this repository's 28-capacitor candidate are alternatives, not additive components: 18 of our capacitor centers fall within 1 mm of an external RAM capacitor center. Their via positions, antipads and supply-drop assumptions differ. Choose one bank, then integrate and check all selected copper together. Keep the current capture and both experiments immutable until that combined result passes.

VTT source/sink regulation and far-end CA/CK termination remain unplaced in the external fixture. Effective capacitance under bias and temperature is unqualified; the nominal per-RAM values are 1.3 µF HS and 44 µF bulk. CPU VDDS_DDR bulk qualification remains a separate gate. VREF distribution includes 0.12 mm local escapes and long inner8 feeds, which still require review against the reference-routing and actual stackup requirements. Regulator startup, complete shared-board return paths, full data/CA/CK routing, timing extraction and DDR initialization/training are not established.

The smallest safe integration step is to freeze the chosen support geometry, correct its known angle/launch failures, prepare a new signal-only routing input from the **actual supported circuit**, and assign a new provenance hash. The existing import adapter expects a signal-capture `capture-report.json` and exactly 78 signal branches; support captures also contain support `_external` traces and use a different report schema. It must explicitly filter the 39 DDR signal terminals per RAM and verify the supported capture rather than accepting a fabricated compatibility report. No support capture is imported or merged by this audit.

## Isolated global-plane integration candidate

`dist/ddr-global-plane-reuse-plan/` combines the local 28-cap bank, 24 earlier RAM drops and four explicitly shared existing vias. It uses the frozen CPU/RAM capture, not the external 35-cap support fixture. `scripts/plan-ddr-global-planes.ts` constructs global GND on inner1/inner5 and DDR 1.5 V on inner3, inside the 64 × 42 mm host board. Every foreign through-via barrel and trace receives a polygon-boolean clearance void; overlapping voids merge. The original local-plane voids remain except eight obsolete ground antipads per ground layer, which are explicitly removed after the corresponding VSS/VSSQ escapes join CPU GND. The report retains each removed hole's exact geometry and reason.

The three resulting planes each have one connected copper region. Independent foreign-copper checks report at least 0.105 mm clearance. All 136 distinct intended ground vias and 68 distinct supply vias have full sampled annulus contact, including all 56 dedicated capacitor vias. These are geometric contacts, not an impedance or fabrication qualification.

The source-pad launch audit separately verifies 50 of the 60 RAM supply/ground balls reach an appropriate plane via within 1.524 mm. VSSQ_D1, VDD_A9, VDDQ_B9, VSSQ_D9 and VDDQ_E9 remain unresolved on each RAM. The candidate is therefore partial: no DDR signoff, effective-capacitance guarantee, complete PDN qualification or fabrication release follows from these plane checks. Reproduce the launch audit with `bun scripts/audit-ddr-global-power-launches.ts`; actual candidate previews are generated by `bun scripts/render-ddr-global-planes.ts`.

The accepted combined snapshot currently retains seven signal routes. The separately saved `dist/ddr-global-plane-reuse-d1-rejected/` eight-route attempt has seven D1-to-support copper conflicts and is excluded. A route passing the original signal-only board check must still pass this combined support geometry check before incorporation. Top, bottom and inner1/inner3/inner5 SVG/PNG previews in the accepted directory come from its actual combined circuit JSON.

The exported candidate also materializes the cap bank's two rail joins as explicit `source_trace` records joining existing capacitor/via ports and their local net IDs to CPU GND and VCC_DDR_1V5. The complete combined copper check passes with an empty external alias map. These additions change only netlist metadata; all PCB geometry remains byte-for-byte identical to the checked seven-route candidate.