0hmX/am3352

docs/ddr-system-progress.md

# Full AM3352 / two-MT41K512M8 system work

Current authoritative status and combined clock/ZQ export: [DDR current status](ddr-current-status.md). Earlier experiments below retain their historical scope.

This is ongoing board integration, not DDR signoff. Local breakout checks do not establish a working memory interface.

## Earlier power59 stage, before the combined clock/ZQ export

`dist/ddr-twenty-one-power59-current` includes completed D12 and D15 hosts and the D15 E7 local escape, preserving both current E3 launches and the inherited inner3 plane-web repair. Candidate object SHA256: `9893a6718f0a0a0b0f7422e99213f10e4cd7d66681ba329e6911834a710db932`. All byte0 DQ0–DQ7 and DM0 match the actual 28.423158 mm DQS0 mean; DM1 matches the 27 mm DQS1 mean. Fresh checks find **21 connected signals**, zero clearance, self-contact, octilinear or joined-turn violations, and **59/60 qualified RAM power launches**. **Twenty-nine interface signals remain unconnected:** byte1 DQ5 plus twenty-eight shared/control signals. This is geometric progress against the frozen capture, not DDR signoff or qualification of the current external RAM adapter.

RAM1 E9 now reaches the existing G8 supply via at (−14.800046, 6.100000) in 1.365568 mm. Moving F8’s ground via to (−14.000046, 6.099900) clears that route while retaining F8’s 0.565685 mm launch. G8 and E9 are exactly two pads on their shared via; all previous 56 qualified launches remain qualified. The new F8 supply-plane opening uses the external 0.107 mm clearance and a separately documented provisional 0.127 mm minimum copper web. Its measured web is 0.128881 mm; all inner2/inner4 saved and host segments retain their prior projected reference coverage. This is not fabrication approval. The remaining power launch is RAM0 E9.

The coupled RAM1 repair now qualifies D1 by moving E2’s supply launch, adding a dedicated C1 supply via, and rerouting the DQ2 and E7 tails around those barrels. All 21 host objects remain exact; their complete lengths reflect the changed local escapes. Three plane updates retain all 57 previous qualified power launches and add no projected reference gaps. Their minimum new webs are approximately 0.128627 mm under the explicit provisional 0.127 mm web and 0.107 mm clearance assumptions.

RAM0 D1 is now qualified using a different C1 landing at (−9.200108, −9.299892) mm. C1, D1 and E2 launches measure 0.565685, 0.565722 and 0.565685 mm. This repair preserves every data trace and host exactly, all 58 prior qualified power launches, and projected reference coverage. The minimum new plane web is 0.128627 mm under the documented provisional assumptions.

The group-aware `interface-completeness.json` audit reports 21/50 unique CPU signals and 21/78 RAM branches connected. A shared signal counts as complete only when both RAM branches connect; this does not qualify fly-by topology or termination.

Full source-pad-to-source-pad planar lengths, independently bound to the current candidate in `current-byte-budgets.json`, are:

| Byte | Signals | Full planar length (mm) |
| --- | --- | ---: |
| 0 | DQS P / N | 28.373159 / 28.473158 |
| 0 | DM, DQ0–DQ7 | 28.423158 each |
| 1 | DQS P / N | 26.950000 / 27.049999 |
| 1 | DM | 27.000000 |
| 1 | DQ0 / CPU D8 | 20.581968 |
| 1 | DQ1 / CPU D9 | 21.723228 |
| 1 | DQ2 / CPU D10 | 18.630231 |
| 1 | DQ3 / CPU D11 | 24.897787 |
| 1 | DQ6 / CPU D14 | 23.869762 |
| 1 | DQ4 / CPU D12 | 22.289882 |
| 1 | DQ7 / CPU D15 | 23.337480 |
| 1 | DQ5 | Unrouted |

The byte nominal budgets remain 28.899838 mm and 27.300100 mm. The DQS means are 28.423158 mm and 27.000000 mm. Several data routes still need matching, and these planar lengths omit package and via delay. Both RAM modules retain their original envelope: RAM0 has a full 72-path cache with six changed paths, B7, C7, C8, E3, E7 and E8 (66 unchanged); RAM1 has seven changed paths, B7, C2, C7, C8, D2, E3 and E7 (65 unchanged). Added padding is zero on every side. RAM0 E8/DQ5 exits world-right at (-6.040077, -8.5) on inner6 with a 45° northeast tangent; its local exit is (-5.959923, 2.0), local-left, southwest tangent. The retained through-via spans all ten layers. RAM1 DM retains the inner2 northeast exit documented below. RAM1 C7/DQ1 (CPU D9) exits world-right at (-6.040077, 3.3) on inner6 with an eastward tangent (0°), local-left at (-5.959923, 3.2) with westward tangent (180°). Its host through-via is (-5.6, 2.9), top↔inner6. D8, D9, D10, D11, D12, D14 and D15 still need length matching to DQS1. RAM1 D2/DQ6 (CPU D14) exits world-right at (-6.040077, 2.5) on inner2 with eastward tangent (0°), local-left at (-5.959923, 4.0) with westward tangent (180°). Its logical launch is top→inner2 on the retained full ten-layer barrel. RAM1 C8/DQ3 (CPU D11) exits world-right at (-6.040077, 2.4) on inner6 with northeast tangent (45°), local-left at (-5.959923, 4.1) with southwest tangent (-135°). Its actual 0.2 mm outward collar clears D9, and its host stays on inner6 with no new via. Both local/world contracts and caches are included in the artifact.

The enlarged DQ2/DQ6 antipad caused a 0.178405 mm projected reference gap beneath DQS0 P. The current board replaces that experimental void with two nominal-clearance circles and a rounded connecting void, restoring full projected DQS0 P coverage on inner1 and inner3 without moving any signal. Each repaired plane restores 0.135147 mm² of copper; restored copper maintains at least 0.1016 mm clearance, and the merged void retains 1.860967 mm web to distinct boundaries. Original baseline voids and all signal routes remain unchanged by that repair. Other signal-via/void coverage gaps are still recorded in `host-reference-coverage.json`. Stackup/impedance, return transitions, complete timing and SI qualification remain outstanding.

Both current E3 escape updates add 0.8 mm of RAM-local length. Byte0 DQ4's host is shortened by 0.8 mm to preserve its 28.423158 mm complete length; byte1 DQ4 is now connected at 22.289882 mm and still needs matching. The inherited inner3 repair removes two 0.003306 mm copper slivers by joining existing voids, retaining one outer copper component. The neighboring webs measure 0.128881 mm. This uses an explicit **provisional 0.127 mm web policy** and the external E3 pour clearance of **0.107 mm**; neither is fabrication approval. The original DQS0 reference repair remains included, and the fresh reference diagnostic reports no newly lost coverage from the sliver repair.

At the nineteen-host milestone, the read-only [72-path envelope audit](../dist/ddr-nineteen-current-e3-metadata-audit/report.json) binds the candidate and input hashes. Both bytes have identical frozen, pre-E3 and post-E3 local centerline bounds: x −5.959923…5.060050 mm, y −4.800092…5.200092 mm. Growth is zero on each side. Including actual cached trace widths and via radii, the envelope also stays fixed: x −6.019923…5.120050 mm, y −4.860092…5.428692 mm. This cache envelope excludes unchanged pads and support copper. The corrected contracts are applied in `dist/ddr-nineteen-current-profile` by `scripts/refresh-ddr-current-metadata.ts`; the report binds both current contract hashes and retains the prior metadata. That metadata-only milestone retained copper byte-for-byte from `dist/ddr-nineteen-current-e3-web-repaired`; subsequent D12, D15 and F8/E9 changes are recorded in the latest evidence manifest.

### Current external RAM adapter compatibility

The external native 72 paths remain unchanged. E3 has now been adopted in both bytes, but the original frozen-capture differences at **E1, E2 and the F7/G7 clock adapters remain unresolved**. Historical read-only comparisons are [current-ram-adapter-changes.json](../dist/ddr-eighteen-d11-connected/current-ram-adapter-changes.json) and [current-ram-source-audit.json](../dist/ddr-eighteen-d11-connected/current-ram-source-audit.json). They compare current external source with the frozen capture; they do not qualify this integrated board against every current adapter. Full interface routing, timing, return-path, impedance and fabrication qualification remain incomplete.

Validation: **187 tests pass**, 47,212 assertions across 60 files; typecheck passes. After the power59 cache binding, all seven focused wrapper/cache/current-trunk tests pass (4,701 assertions). Exact current-board previews and their `render-provenance.json` are saved in the accepted directory.

The public `DdrMemoryBoardProfile` wrapper loads both complete physical caches without repeating host adaptation or adding local pours. Its rendered tests verify all 144 source-owned exits, route points, physical layers and full-depth barrels across cardinal placements. RAM0 still needs twenty-two documented board power replacements and RAM1 twenty-four plus host routes and support copper to reproduce the accepted board. See [wrapper API and limitations](ddr-memory-board-profile.md). All four CPU profiles pass rendered angle/junction checks; the three DDR variants also pass rebuilding, reference-plane, rotated-reuse and shorts checks.

### Remaining D1 launch constraint

The relocated E3 launch frees a potential D1 ground-via site. Its barrel and explicit ground-plane refills pass clearance and sampled annulus checks, but the short top-layer launch crosses C1/D2 copper. The existing winding solver exhausted 37,463 reachable states without a route to that site; this is a bounded grid-search result, not a proof over all geometry. The trial is rejected, all nineteen hosts remain unchanged, and the power count stays 56/60. Evidence: `dist/ddr-d1-freed-via/README.md` and `dist/ddr-d1-freed-via-winding/report.json`.

D12 uses a full-depth host via at (−5.5, 5.0) mm to connect its original RAM inner4 escape to CPU inner6. Its complete path measures 22.289882 mm. D15's RAM E7 escape now exits world-right at (−6.040077, 4.1) mm on inner6, eastward tangent; local-left at (−5.959923, 2.4) mm, westward tangent. The original pad and via are retained, and the actual 0.2 mm outward collar clears the full twenty-one-host board. D15 now connects through a host via at (1.0, −0.4) mm, logically top↔inner6, with a full planar length of 23.337480 mm. It remains below the 27.3001 mm absolute budget but needs matching to DQS1. The [current full-width cache envelope audit](../dist/ddr-twenty-one-power59-current/cache-envelope-audit.json) proves no E7 envelope growth including actual trace widths and via radii; both cache contracts are rebound to this candidate.

### Prior byte1 D14 same-layer limit

The current-board winding attempt for DDR_D14 (RAM1 DQ6) exhausted 300,000 search states without a route. A one-million-state run found a clearance- and bend-valid inner4 route, but its complete length is **45.534950 mm**, exceeding **27.300100 mm**. Its host alone is 32.443324 mm; RAM and CPU escapes contribute 6.246857 and 6.844768 mm. The candidate is rejected and does not increase the accepted connection count. Evidence: `dist/ddr-d14-current-host-1m/report.json`. The current sixteen-host board resolves this with the revised RAM inner2 escape and a checked CPU transition; the excessive inner4 detour remains rejected. D11's first proposed exit at y=2.9 failed its outward collar against the D9 barrel. The current lower inner6 exit at y=2.4 and its northeast collar pass actual checks, and the connected D11 host is included in the eighteen-host count.

## Prior board: DM1 right-facing escape

`dist/ddr-twelve-dm1-facing` preserves eleven hosts from the DQ1 milestone and replaces DM1 with a **22.054969 mm** complete path, below its **27.300100 mm** nominal maximum. It still contains twelve connected signal nets and 56/60 qualified RAM power launches. DM1 is not yet matched to a qualified DQS1 target; the current DQS1 pair remains overlong.

RAM1 B7 exits the module's world-right side at **(-6.040077, 2.1) mm on inner2**, with a **45° northeast final tangent**. With RAM1 rotated 180°, the local exit is **(-5.959923, 4.4) mm**, on the local-left side, tangent -135°. The .12 mm route retains the existing RAM top-to-inner2 transition; its physical barrel spans all ten layers. The host adds no via. All 71 other RAM1 cache paths are unchanged, and added padding is zero on all four sides. The inherited RAM0 cache is retained separately. See `ram-byte1-exit-contract.json` and `ram-byte1-facing-progress.trace-paths.json` in that artifact.

Fresh full-board clearance, endpoint-only connectivity, nonlocal self-contact, route angles and cross-trace junction checks pass. The new DM1 host centerline has continuous rendered reference coverage on inner1 and inner3. These checks do not establish full interface timing, impedance or SI compliance.

The first independent DQ2/DQ6 merge had four copper-clearance violations. Subsequent joint rerouting resolved them; the latest fourteen-signal board above also includes the relocated DQ4 transition and successful DQ5 host. Length matching remains incomplete.

## Prior board: DQ1 overlength removed

The preceding self-contained board is `dist/ddr-twelve-dq1-partial-timing`. DQ1's former 37.586558 mm route is replaced by a 28.423158 mm route that matches the actual DQS0 mean. Its RAM C7 escape now exits world-right at (-6.040077, -8.1) mm on inner6, with an eastward final tangent. A conventional host through-via at (1.29, -1.6) mm joins the CPU inner2 route to inner6. Existing inner5 ground provides the adjacent rendered reference for inner6; full stackup and return-path qualification remain incomplete.

All twelve signal nets remain connected. Exact replacement witnesses cover the RAM trace and exit, retirement of the old DQ1 host, the new host, three plane antipads and the final one-trace tuning. The other eleven hosts are preserved. Actual clearance, source-owned endpoint contacts, self-contact, all route angles and all junctions pass; the refreshed RAM power audit remains **56/60**. The full RAM0 cache has 72 paths: B7, E7, C8 and C7 changed, 68 unchanged, with zero additional padding on every side. Source ownership and full DQ1 length were independently remeasured. The current 22-member length audit is `dist/ddr-twelve-dq1-partial-timing/current-byte-budgets.json`.

DM0 and DQ0/1/3/4/7 each match the 28.423158 mm DQS0 mean. DQ2 is still overlong; DQ5 and DQ6 remain unhosted in the accepted board. Thirty-eight interface signals, four power launches and full interface timing/SI remain unresolved. Validation: 169 tests pass; typecheck passes.

### Rejected continuation candidates

DQ5's first inner6 escape and host passed against the preceding board, but its local escape collided with the new DQ1 escape at five copper contacts. That version was never merged. A new DQ5 escape with the complete tuned DQ1 reserved clears the actual board, but its host totals **29.916080 mm**, exceeding the 28.899838 mm nominal limit by **1.016242 mm**. Both weighted and unweighted existing-solver runs produced the same route. The detour clears the existing DQ4 inner6 approach and through-via at (0.875, -5.619) mm. Thirteen geometric connections in this diagnostic are not thirteen accepted routes. Evidence: `dist/ddr-facing-d5-after-dq1`, `dist/ddr-dq5-after-dq1-host` and `dist/ddr-dq5-after-dq1-host-unweighted`.

DQ6's transition at (0.89, -6.8) mm passes actual full-barrel checks, but the continuation again exhausts its reachable search component after 495 states, even after the old DQ1 inner2 host is removed. No DQ6 host is accepted. Evidence: `dist/ddr-dq6-after-inner6-dq1-host`.

Earlier DQ5 inner2 searches failed on both 0.1 mm and 0.02 mm grids. The unrestricted fine grid exceeded the installed API's 160,000-node limit before searching; a restricted 156,798-node region did run and exhausted 419,635 states. These are bounded search outcomes, not proofs that the layer is impossible.

## Prior milestone: twelve connected signals, D0 and D3 matched

The prior self-contained board is `dist/ddr-twelve-byte0-partial-timing`. D0 and D3 each measure 28.423158 mm, matching the retained DQS0 mean. D0 keeps both host vias; D3 connects through a new conventional through-via at (1.29, -4.8) mm. Its CPU-side path begins on inner2 at (2.69, -2.8), runs west to (2.09, -2.8), then diagonally to (1.29, -3.6) and south to the via; the remaining host route uses inner4 to reach the RAM exit. Every turn remains at most 45°.

The combined board passes actual conductor clearance, all-route angles, all junctions, 24 source-owned endpoint contact witnesses and nonlocal host self-contact checks. All twelve hosts are physically connected. The fresh RAM power audit remains **56/60**. The assembly chain records one D0 retune, three plane antipad replacements, one added D3 host and its subsequent single-trace tuning; unrelated parent elements retain their exact values and order. The full 72-path RAM0 cache and actual exit contract are included.

| Complete planar member | Length (mm) |
| --- | ---: |
| DQS0 P | 28.373159 |
| DQS0 N | 28.473158 |
| DQS0 mean | 28.423158 |
| DM0, DQ0, DQ3, DQ4, DQ7 | 28.423158 each |

D3 originally connected at 28.033321 mm in `dist/ddr-twelve-d3-connected`; the final chamfered tuning adds 0.389837 mm while preserving its via, endpoints and width. The result is below the 28.899838 mm nominal limit. The reference-centerline diagnostic finds only own-via antipad gaps, including the new D3 via; this does not validate its return path, dielectric stackup or signal integrity. Thirty-eight signal nets, four power launches and complete interface timing remain unresolved. The fresh 22-member length audit is `dist/ddr-twelve-byte0-partial-timing/current-byte-budgets.json`.

A separate inner2-only D3 escape attempt at RAM exit (-6.040077, -8.6) returned no alternative after 36,824 search states. This bounded result does not prove that layer impossible; the accepted board uses the verified transition above.

### D3 return-path geometry investigation

Against `dist/ddr-twelve-byte0-partial-timing`, the nearest existing source-owned GND through-via that contacts both inner1 and inner5 is `pcb_via_75` at (4, -5.6) mm, 2.825615 mm from D3's signal transition. Fresh annulus checks report 32/32 samples in each ground plane. No electrical maximum-distance criterion or SI pass is inferred from this distance.

The bounded closer-stitch searches did not produce a valid addition. Fifteen 0.9 mm-radius placements failed copper or plane constraints; eight northwest/southwest placements at 0.65/0.75 mm failed the separate-antipad planner. An additional experiment used the installed Flatten boolean subtraction API to merge overlapping power-plane voids: four 0.65 mm placements then passed single-component plane continuity and minimum-web checks, but all four collided with actual signal copper. Four 0.75 mm placements left insufficient web. Thus merged antipads are supported, but those specific positions remain unusable. No stitch or plane change was accepted. Evidence is in `dist/ddr-d3-return-transition-audit`, `dist/ddr-d3-return-transition-closer-audit` and `dist/ddr-d3-merged-antipad-experiment`.

## Prior milestone: eleven connected signals with partial byte-0 timing

The prior self-contained host board is `dist/ddr-eleven-byte0-partial-timing`. DQ7 connects, and four host traces have been explicitly retuned: the two DQS0 legs, DQ4 and DQ7. All eleven hosts pass actual conductor clearance, strict 45° geometry, complete junction checks and source-owned terminal-only contacts. The new nonlocal host-wire self-contact audit also passes; it excludes local corner fill and does not claim field-coupling qualification. The actual power audit remains **56/60** RAM launches. Validation at this milestone: **163 tests pass**, and typecheck passes.

| Complete planar member | Length (mm) |
| --- | ---: |
| DQS0 P | 28.373159 |
| DQS0 N | 28.473158 |
| DQS0 mean | 28.423158 |
| DM0 | 28.423158 |
| DQ4 | 28.423158 |
| DQ7 | 28.423158 |

These members fit the 28.899838 mm nominal reference. Other data members remain short, overlong or missing; matching this subset does not qualify a whole byte or account for stackup-dependent propagation and via delay. DQ12 remains explicitly unrouted following its invalid-loop finding. Thirty-nine signal nets and four power launches remain incomplete.

The compatible D3 escape revision is in `dist/ddr-facing-d3-partial-timing`. Its eleven retuned hosts are exact copies of the self-contained parent (verified parsed equality and both file hashes in `final-parent-equality.json`). The 72-path RAM cache changes B7, E7 and C8 only; 69 paths are preserved. D3 exits right at (-6.040077,-9.3) mm on inner4, with no new barrel or padding. Its RAM + CPU + optimistic host floor is 27.213220 mm. D3 still needs an actual host route to its CPU inner2 exit.

For the next transition plan, D3 and DQ7's CPU exits share (2.69,-2.8) mm on different layers (inner2 and inner4). A through-via directly at that common coordinate would contact both nets. Transition placement must therefore be checked against both the fixed escapes and current host approaches; the per-layer endpoints alone do not reserve a legal through-via location.

A bounded below-side transition diagnostic checked 50 candidates against this actual D3 candidate. All met the angle rule but collided with existing copper; the southwest launch crosses the shortened DQS0 pair on inner2. No candidate reached plane repour or was added to the board. `dist/ddr-d3-actual-transition/transition-plan.json` records exact collision shapes and input hashes. This rejects that launch template, not all possible D3 transitions.

### Escape lengths before the DQ1 revision

`scripts/audit-ddr-current-byte-budgets.ts` remeasures all 22 byte members from the current candidate's source-owned pads and exact saved endpoints, verifies all existing host topology, and records input hashes. Its output for the D3 candidate is `dist/ddr-facing-d3-partial-timing/current-byte-budgets.json`. Seven members exceed their byte's nominal budget even at the obstacle-free octilinear host floor:

| Byte | RAM terminal | Floor excess (mm) |
| --- | --- | ---: |
| 0 | DQ1 | 4.207226 |
| 0 | DQ5 | 0.952168 |
| 1 | DM | 0.853189 |
| 1 | DQ1 | 0.379329 |
| 1 | DQ3 | 1.656704 |
| 1 | DQ5 | 2.786178 |
| 1 | DQ7 | 1.704790 |

These members require escape or placement changes; shortening host copper alone cannot meet the present nominal limits. The terminal numbers are local to each x8 RAM. Positive headroom for other members remains optimistic: it excludes obstacles, tangent restrictions and propagation through vias/packages.

## Prior milestone: ordered DM0 connects within nominal length

`dist/ddr-dm0-ordered-host` replaces the previous mask route with a host continuation from the ordered RAM0 exit at y=-7.1 mm. It starts from nine retained host nets after explicitly retiring both the old mask host and invalid DQ12 host, then adds the new mask host for ten connected nets. Twenty host/fixed contact pairs are all authorized terminal joins; there are no detected interior contacts. Full copper, angle, junction and endpoint-contract checks pass.

The self-contained export includes the 72-path RAM cache, exact exit contract, replayable source provenance, preserved host-route report and a fresh **56/60** RAM power-launch audit. Validation: **154 tests pass**, and typecheck passes.

The actual mask path is **28.423158 mm** (RAM 13.816792 + host 10.959723 + CPU 3.646643), below the **28.899838 mm** nominal reference by **0.476680 mm**. Its host adds no via. Both RAM mask and DQ7 exits now have the same vertical order as their CPU endpoints. DQ7 is still unhosted; this result does not prove its continuation or complete byte timing. The old DQ12 remains explicitly absent.

## Prior seed: ten connected signals, 56 power launches

`dist/ddr-composite-ten-seed` explicitly removes the invalid DQ12 host trace while preserving all other candidate objects. Ten host signal nets remain connected and pass the endpoint contract, strict angles, all-junction checks and host/fixed unintended-contact check. The independent RAM pad-to-plane audit still qualifies 56/60 launches. This is a routing seed with incomplete timing, not DDR acceptance; forty signal nets remain unrouted.

The next RAM0 DQ3 escape is reproduced by the ordinary planner at `dist/ddr-facing-d3-reproduced`, and its transplant into the latest composite is checked separately in `dist/ddr-facing-d3-feasibility/latest-composite-check.json`. It exits world-right at (-6.040077,-9.3) mm on inner4, reuses the existing via, and adds no padding. RAM + CPU escapes plus obstacle-free host floor total 26.071583 mm, below 28.899838 mm nominal. The CPU exit is inner2, so a real host route still requires a layer transition and full verification.

The planner now materializes the winding solver's implicit via departure as an explicit wire vertex at the retained via center. It retains the exact pad launch and physical barrel, rejects extra vias or non45 departures, and performs the same full copper checks. This fixes an output-representation rejection rather than relaxing a routing rule.

## Topology audit: DQ12 must be rerouted

The eleven-net candidate's DQ12 host route reconnects to its own RAM1 saved escape and via. Ten non-endpoint host/fixed contact pairs belong to this one net; the other ten hosts have only endpoint contacts in the initial audit. The RAM escape and host trace explicitly share source_port_1004, so the copper checker correctly treats them as the same net—but absence of a short circuit does not prove a valid point-to-point topology.

The route comes within 0.000054 mm of the retained RAM via center and physically overlaps its annulus. The nominal loop through the saved exit is approximately 9.450590 mm. Consequently, the previously reported 49.150455 mm sum is not a physical serial-path length, and DQ12 must not be accepted for timing or used as a qualified seed. Original artifacts remain available as diagnostic evidence.

New routing projection reserves same-net fixed copper outside the final 0.25 mm of each actual terminal approach. This only changes the solver's obstacle projection; actual copper is retained and independently checked. Exact host-reference projection also identifies the DQ12 excursion through the saved RAM via's antipad on both adjacent planes. All other observed host reference gaps belong to their own host transition-via antipads; this does not verify return-via placement, trace-width field coverage, or stackup impedance.

DQ7's current inner4 exits reverse order with DM0 between RAM and CPU. Searches at 300,000 and 600,000 states found no same-layer continuation. An ordered RAM exit revision is being tested; no search-budget failure is treated as proof of impossibility.

## Historical eleven-signal geometry candidate — DQ12 rejected by topology audit

`dist/ddr-facing-progress-45` combines the accepted DM0 host route, two CPU-facing RAM0 exits (DM/B7 and DQ7/E7), and the latest power repairs. **11/50 signal nets connect and 56/60 RAM power launches reach their reference planes within the launch limit.** The revised traces and host routes have zero clearance, angle or joined-bend violations. DM0 measures **25.413042 mm** including both escapes, below its 28.899838 mm nominal reference. DQ7 has only a revised escape; its host route remains absent.

The 72-path experimental RAM cache changes exactly two paths and preserves 70. Both revised exits are world-right/local-left at the frozen 180° placement, on inner4, with southeast world tangents. They reuse the physical through-vias and add no padding. Exact endpoint coordinates, tangents and layer mapping are in the candidate's `exit-contract.json`; this remains composite provenance, not a refreshed capture or released default profile.

The stronger audit of **all** trace junctions found an existing CPU L6 pad junction that individual-route checks miss. The K6 approach is now corrected in all four reusable CPU profiles. All four rebuilt profiles pass both per-route and complete junction audits, with all 313 saved fanout paths preserved. The derived `ddr-facing-progress-45` candidate applies an exact one-trace correction and widens that supply link to 0.1016 mm. It passes the all-candidate route and junction audits, with zero new-copper clearance violations and all eleven host nets and 56 power launches preserved. The frozen integration capture retains its historical geometry for reproducibility. The remaining four RAM power launches (D1 and E9 on each RAM) failed 800 tested shared-via approaches: retained adjacent pads and opposite-rail barrels leave about 0.012 mm clearance in the best tested routes, below 0.1016 mm. This bounded search does not prove every alternative impossible.

Complete byte timing still fails on existing overlong host routes. Thirty-nine signal nets, four power launches, remaining profile revisions, return paths, impedance and fabrication validation remain unfinished. The historical milestones below describe earlier candidates.

## CPU-facing mask profile and 54 power launches

Validation: **129 tests pass**, and typecheck passes.

The latest isolated candidate is `dist/ddr-facing-dm0-power54`. It preserves **10/50 connected host signal nets** and qualifies **54/60 RAM supply/ground launches**. Both B9 balls now share the existing A9 via at 1.027917 mm, with exactly two balls per via and no new barrels. All combined physical checks pass.

A new full 72-path RAM0 cache changes only DM/B7: its exit moves to the CPU-facing edge on **inner4**, using the existing physical via. It passes source-copper, schema, 45° and unchanged-envelope checks. Its optimistic total length drops below the placement-derived nominal reference: **25.044 mm versus 28.900 mm**. This is the first verified escape redesign; it is not a completed mask host route or a complete DDR profile release. The other nine problematic exits and the existing overlong host routes still need work. See [CPU-facing exit details](ddr-facing-exit-progress.md) for sides, tangents, layer, reproduction and limitations.

## Latest combined candidate — ten signals and 52 power launches

`dist/ddr-integrated-ten-power52` preserves all ten connected host signal paths and raises the actual RAM pad-to-plane launch result to **52/60**. Two new VDD_A9 connections each reach a full-depth via within 0.55 mm. Four unused bottom ground tails are removed after their already connected ground vias; six trace changes and two plane changes have exact before/after replacement witnesses. All other parent elements remain exact. The complete candidate has zero copper/angle/join violations and uses no external aliases. Eight layer previews are provided with the candidate.

Validation: **123 tests pass**, and typecheck passes. This does not override the nominal-length failures below. Forty signal nets, eight RAM power launches, exit-profile redesign, full timing, return paths and the remaining electrical/fabrication gates are unfinished. The new support result is validated as an explicit replacement chain over its parent; future routing must preserve and validate that chain instead of treating the original-only support loader as sufficient.

## Ten-net geometry candidate and nominal-length finding — 2026-09-11

`dist/ddr-integrated-ten` adds DQ12 (RAM1 DQ4) to the prior nine-net geometry candidate. All ten supplied nets connect with zero copper violations, angle violations or joined-bend violations and no external aliases. Three new plane antipads are checked and all previous plane contacts are preserved. The actual RAM power-launch audit remains 50/60. This is a **geometry diagnostic candidate, not a DDR-qualified layout**: DQ12 measures 49.150455021 mm including the breakouts and exceeds the byte's placement-derived nominal-length reference.

The original winding solver preserved direction inside its grid but initialized every escape connector without an incoming direction, and did not validate the connector-to-escape turn at a completed goal. That allowed a 135° turn at the DQ12 RAM collar. The pinned dependency patch now carries the connector direction into the grid state, retains the matching starting connector when reconstructing a route, and rejects sharp turns across connectors and same-layer source escapes. Three regression tests cover the observed reversal, duplicate vertices and a complete search that must initially follow a fixed eastward escape. The patch is recorded against the exact GitHub dependency in package.json/bun.lock and reproduced by bun install.

Transition routing now begins at the actual RAM escape tangent and ends at the verified CPU via; the reversed CPU approach is joined through that physical layer transition. The search extends to x=4 mm rather than stopping at the CPU exit boundary x=2.69 mm. No existing obstacles or final checks are removed. Transition planning accepts an optional `above`/`below` family, and the same-layer adapter validates its actual target layer rather than hardcoding inner2.

The source-owned ball audit gives DQLM0=28.899838 mm and DQLM1=27.300100 mm. TI SPRS717L Table 7-69 places the nominal-length parameters in its MAX column; the 25 mil skew budget is not an additional absolute-length allowance. Existing DQ1/DQ2 and the new DQ12 route substantially exceed these references. Increasing strobe length to match long detours cannot establish compliance. Exit direction/order and fixed-escape length must be reconsidered before further tuning. See `dist/ddr-integrated-nine/dqlm-audit.json` for actual pad identities, coordinates and the distinction between paired Manhattan maxima and a conservative independent-axis envelope.

The lower-bound audit independently reproduces all 22 captured byte-member floors. Each byte's DM and local DQ1/3/5/7 exits face left, away from the CPU, and their fixed escapes plus obstacle-free octilinear continuation already exceed paired DQLM. Several exceed even the more conservative independent-axis envelope. Those frozen exits need a profile revision before host routing can meet this nominal reference. DQ12 instead has a 21.425446 mm floor: its 49.150455 mm route is a topology/routing-order problem, not a demonstrated fixed-exit impossibility. The board evaluator now requires per-byte DQLM measurements and rejects a fully matched but overlong byte independently of skew.

## Current nine-net candidate — 2026-09-11

Validation: **114 tests pass**, and typecheck passes.

`dist/ddr-integrated-nine/candidate.circuit.json` adds **DQ2**, bringing the self-contained integrated result to **9/50 connected signal nets**. DQ2 uses a conventional 0.4572/0.254 mm through-via at (2.29, −1.60) mm, transitioning from the CPU top-layer exit to RAM byte-0 inner2. Three explicit antipads were added on inner1, inner3 and inner5. The assembler regenerates and compares those hole changes, rechecks every previously connected ground/supply via annulus, and runs the complete combined copper check with no external aliases. All checks pass; the RAM power-launch count remains **50/60**.

The first 100,000-state winding search did not complete DQ2. A bounded 300,000-state attempt found a route; no angle or clearance rules were relaxed. Independent extraction measures DQ2 at **43.032146614 mm** including both breakouts, so complete byte timing remains unfinished. The supported D3 retry with DQ4 tuning removed also found no path at its 100,000-state limit; the original tuned candidate remains available. These failures are search-budget results, not proof of physical impossibility.

New reusable steps are `plan-ddr-data-transition.ts`, `route-ddr-transition.ts`, and the optional transition-directory argument to `assemble-ddr-supported-candidate.ts`. Proposed transition barrels first pass a fast conductor check, then explicit plane-clearance and full-candidate checks. No partial transition is counted as a completed signal net. Forty-one signal nets, ten RAM power launches, full interface timing and the remaining acceptance gates still need completion. The eight-net result below is the prior accepted milestone.

### Uniform bend rule and reduced-spacing audit

The same strict angle gate applies to native, ddr_left, ddr_top and ddr_bottom, including saved signal paths and fixed support traces: only horizontal/vertical/45° segments, and at most 45° direction change per bend. Exit side, outward direction, final tangent and copper layer remain documented for every profile in `signal-exits.md`. Accepted integrated routes also pass the full-copper joined-bend check.

The nine-net candidate now has `reduced-spacing-audit.json`, measuring the union of actual same-layer centerline intervals below the applicable 3w/4w DDR spacing. Differential mates are excluded from this comparison because they require a separate impedance/pair check. The largest measured exposure is DQ2 at 12.181773926 mm, below the 31.75 mm allowance in SPRS717L Tables 7-68/7-69. This covers available DDR trace copper only; incomplete routes, unrelated I/O, pads/vias, reference continuity and SI remain outside this result. It does not establish whole-interface acceptance.

The supported D3 search also failed at 300,000 states. A legal D6 layer-transition candidate at (1.29, −4.80) mm passed copper and plane checks, but its 300,000-state continuation search found no complete route. Neither attempt changes the accepted nine-net candidate or counts as a tenth connected net. These bounded failures do not prove physical impossibility.

## Current integrated candidate — 2026-09-11

Validation: **109 tests pass**, and typecheck passes. This includes preservation of the original netlist when extending the support candidate. These checks do not establish full DDR electrical acceptance.

`dist/ddr-integrated-eight/candidate.circuit.json` combines **eight connected DDR signal nets**, 28 RAM capacitors, 28 repaired/reused supply launches and the global GND/DDR1.5 planes. The complete candidate passes copper clearance, strict 45° headings/turns and connectivity checks **without external net aliases**. Capacitor rails have explicit source-trace joins. Original source-net, source-port and source-trace identities are preserved; a new regression check rejects undeclared changes to the captured netlist.

D1 was rerouted with the actual capacitor and power-drop obstacles included. The accepted supported route replaces the earlier D1 path that collided with seven support objects. Its full planar length is **37.586557904 mm**, so byte timing remains incomplete. The same-layer D3, D13 and D14 attempts returned no candidate within their bounded searches; this does not prove those nets unroutable.

The integrated actual-pad audit verifies **50/60 RAM power/ground launches** reach their intended continuous plane within 1.524 mm. Ten launches remain unresolved. All 56 capacitor vias contact their rails. Eight layer previews and independent timing measurements are alongside the candidate. Remaining work includes 42 signal nets, the ten launches, complete byte/clock/address timing, termination/VREF/VTT support, fabrication parameters and SI validation. No DDR signoff is claimed.

Reproduce assembly with `scripts/assemble-ddr-supported-candidate.ts`; route a same-layer data net using `scripts/route-ddr-winding.ts CAPTURE HOST_BUNDLE OUTPUT SUPPORT_CIRCUIT DDR_Dn`. The support candidate is verified against the captured copper and netlist before routing, and its hashes are checked again after routing. All accepted new copper must pass the full combined physical predicate. Earlier reports below are retained as historical evidence and should not be mixed into this integrated result.

## Prior milestone: seven connected signals — 2026-09-11

The current integration capture is `dist/ddr-system/host-taps-54af3e346b5e`: CPU at (12,0) mm and the two RAMs at (−12,−6.5) and (−12,+6.5) mm, each rotated 180°. Earlier captures and router diagnostics below are historical and must not be combined with this geometry.

**All four CPU profiles now pass the user's strict routing rule:** horizontal/vertical/45° segments only, with no bend sharper than 45°. The audit was run on both saved/fixed paths and each complete rendered profile. Each profile has 313 saved paths plus 173 fixed support routes. The 126 corrected capacitor stubs are included, not exempted. Both authoritative RAM caches (`am3352-byte0` and `am3352-byte1`) also pass: each has 72 paths, 241 wire segments and 72 bends, with maximum turn 45° and no heading violations. The newly rendered RAM capacitor routes and accepted early supply drops are straight; tuned strobe and D0 candidates also pass the strict heading and joined-bend checks. Rejected raw autorouter output remains unaccepted and is not covered by these passing statements.

| Current artifact | Verified result | Remaining scope |
|---|---|---|
| `data-exact-width/candidate.physical.json` | Four tuned DQS nets plus DDR_D0, DDR_D4 and DDR_DQM1: **7/50 complete nets**, zero copper/angle/join violations | 43 signal nets remain incomplete; no full-byte delay or SI signoff |
| `dist/ddr-ram-decoupling-plan/` | **28 capacitors**, 56 dedicated through-vias, 56 local capacitor-to-via traces; placement and all-layer shorts pass | Effective capacitance, parent ground aliases and complete PDN connections remain unverified |
| `power-drop-exact-width/accepted-candidate.json` | **24 of 38 missing early supply drops** have a clean physical candidate, checked against the capacitor placement, original copper, modified reference planes and final seven-net host bundle | **14 drops remain unresolved**; this candidate is not applied to the source RAM package |

These are distinct, provenance-bound partial candidates. The `power-drop-exact-width/host-seed-upgrade.physical-report.json` checks the 23-drop candidate with the exact-endpoint, uniform-width seven-net host bundle, 28 capacitors and modified reference planes. The report records the host bundle hashes and has zero copper/angle/join violations. This remains partial: full DDR acceptance is false.

A subsequent 60-second bounded 45° dogbone search increased the accepted supply drops from **16 to 19 of 38**. See `power-drop-dogbones/accepted-candidate.json` and `accepted.physical-report.json`. The checkpoint preserves search progress and collision witnesses; **19 drops remain unresolved**, and stopping this candidate search does not prove those launches impossible. The combined report reserves the final seven-net host bundle and passes the strict angle check. The earlier straight-only results below are retained as history.

The next bounded search against that exact-width host bundle added RAM1 VSS_J9, reaching **24/38 power drops**. `power-drop-exact-width/accepted.physical-report.json` verifies the 24-drop combined candidate with zero clearance, heading or joined-bend violations. Fourteen remain unresolved; all 23 previous accepted drops remain unchanged.

### Verified DQM1 and DQ4 planar tuning

`data-d4-tuned/candidate.physical.json` is the latest seven-net signal candidate. It preserves the corrected endpoint/width contract and adds explicit 45° tuning excursions to DQM1 and DQ4. DQM1 full planar length is **31.141674266 mm**, matching the byte-1 strobe mean; DQ4 is **34.063314664 mm**, matching the byte-0 strobe mean. The added lengths are 1.824788344 mm and 13.294650502 mm respectively. Each was independently re-extracted from the actual connected centerlines and checked against all original copper. Both strobe pairs remain unchanged.

These measurements improve two partial routes, not the complete byte acceptance. DQ0 remains short, its unnecessary top-layer detour remains, and the other data/mask routes are incomplete. Planar equality does not account for differing via delay or dielectric propagation. `scripts/tune-ddr-data-mask.ts` preserves original endpoints and vias, searches bounded chamfered excursions, and emits copper only after physical and extracted-length checks pass. It accepts optional byte/terminal arguments for DQ or mask tuning.

### Exact endpoints, widths and independent timing audit

`data-exact-width/` is the latest seven-net geometric candidate. Solver-rounded RAM endpoints on D4 and DQM1 were anchored to the original breakout coordinates before regenerating strict 45° paths; all host wire widths are now 0.12 mm. Original-copper checks still report seven connected nets and zero clearance, angle or joined-bend violations. The independent RAM-project graph audit now measures all seven paths and reports no endpoint-disconnection or width errors.

That independent audit also exposes why copper connectivity is insufficient. Full planar DQ0 is 25.211467 mm against a DQS0 mean of 34.063315 mm; DQ4 is 20.768664 mm. DM1 is 29.316886 mm against a DQS1 mean of 31.141674 mm. These fail the intended byte matching budget, and DQ0 adds two host vias through an unnecessary top-layer detour. The data candidates therefore require replacement or tuning; they are not timing-qualified routes. DQS pair geometry remains unchanged. The source and report are `data-exact-width/{candidate.physical.json,physical-report.json,independent-host-audit.json}`.

A provenance-checked power-drop search resumed without repeating prior trials and reached **23/38 accepted drops**, with 15 unresolved. The earlier 19-drop count describes the preceding checkpoint. Changes to a reserved host bundle require a fresh combined copper check before a search checkpoint can adopt its new hash.

### Tuned strobes and the first data route

`dqs-tuning-final/` replaces the initial short strobe corridors. Complete planar lengths, including both escapes, are **34.013315/34.113314 mm** for DQS0 and **31.091675/31.191674 mm** for DQS1. Each pair has approximately 0.100 mm full planar skew and 0.971859 mm host uncoupled length per leg. Both pairs use their assigned layers, add no vias, and pass the physical and 45° checks. These are local geometric timing allocations; the remaining data/mask routes and actual stackup delay still determine final byte acceptance.

`data-d0-normalized/` preserves those four strobe traces as a hash-checked immutable seed and adds DDR_D0 (`source_trace_575`). Its physical report confirms all five complete package-pad connections but correctly retains `valid: false` because the other 45 nets are missing.

The next bounded pass produced six raw routes. Full normalization accepted only DDR_D4 and DDR_DQM1; DDR_DQM0, DDR_D1, DDR_D2 and DDR_D7 failed the physical candidate checks. `data-bounded-full-normalized/` preserves the five-net seed unchanged and verifies **7/50 connected nets**, with no clearance, angle or joined-bend violations. D4 and DQM1 host lengths are 11.583061 and 20.913973 mm, excluding both saved fanouts. The incomplete connectivity still makes overall acceptance false.

### RAM decoupling placement candidate

`plan-ddr-ram-decoupling.ts` produces 12 nominal 100 nF capacitors and two nominal 22 µF bulk capacitors per RAM. The HS parts use the rendered 0201 footprint; bulk parts use 0805. Every capacitor has two dedicated 0.4572/0.254 mm full-depth vias. No capacitor vias are shared. All 56 rendered local traces are horizontal or vertical, with zero bends and zero arbitrary headings.

The actual new pads, traces and full via barrels clear the original capture and tuned DQS copper by at least **0.111292 mm**. Maximum HS capacitor-center distance is **3.577616 mm to an eligible power ball** and **3.298357 mm to an eligible ground ball**, below 3.81 mm. The longest capacitor-pad-to-own-via connection is **0.7375 mm**, below 2.54 mm. Actual courtyard placement has no emitted errors, and all-layer shorts pass. The bulk centers are (−15,−12.7)/(−9,−12.7) mm for RAM0 and (−15,+13.5)/(−9,+13.5) mm for RAM1.

The reference planes participate explicitly. `candidate-reference-planes.json` adds **36 power-via antipads**, nine per local ground plane. The old outer boundaries, holes and captured routes remain unchanged. New holes are contained and disjoint, with at least 0.1524 mm copper web, and the new power barrels pass clearance against the resulting polygons. The ground vias require explicit connection to the existing RAM ground aliases when integrated; neither geometric contact nor this candidate creates a complete parent PDN.

Nominal capacitance is not effective capacitance. The 12 × 100 nF bank must retain at least **0.85 µF** (70.83% of its nominal total), and each two-22-µF bulk bank must retain at least **20 µF** (45.45%). Exact parts, DC-bias/tolerance/temperature data and the complete power network remain required. CPU VDDS_DDR bulk requirements are separate.

### Early RAM supply connection vias

The original capture has **38 outer-column supply/ground escapes without a connection via**. The 1.524 mm ball-to-connection-via requirement applies to those device launches, not to the separate capacitor vias. A nearby capacitor therefore cannot make this original launch gate pass.

The bounded straight-stub search accepts eight changes per RAM: `VSS_J1`, `VDD_K1`, `VSS_L1`, `VDD_M1`, `VDD_K9`, `VSS_L9`, `VDD_M9`, and `VSS_N9`. Most use a 0.55 mm launch; K1 uses 1.225 mm and L1 uses 0.90 mm. All 16 replacement paths are straight and retain the original pad endpoint. Their full physical candidate has no clearance, heading or joined-bend violations, with minimum clearance **0.1016 mm**. Its reference-plane output retains all capacitor antipads and adds the supply-drop antipads explicitly.

The remaining **22 launches** collided with existing copper throughout the tested straight-stub range. That is a failure of this bounded candidate family, not proof that the package is unroutable. They need a different local path or coordinated layout change. Supply-plane connectivity, VREF/ZQ/termination, full host routing, complete timing and impedance checks are still unfinished.

## Historical full signal fixture

```sh
bun scripts/capture-ddr-system.tsx /path/to/mt41k512m8da-107-it-p-fanout outward_north
 # Use the capture directory printed by the preceding command (includes a content hash).
bun scripts/route-ddr-system.ts "$capture_dir" 120 --obstacles-only --pipeline=4 --effort=4
```

The fixture declares all **78 branches / 50 nets**: 22 byte-specific nets and 28 shared nets (including reset), with an actual CPU and two x8 RAM devices. CPU center is (12,0) mm, RAM centers (-12,+8) and (-12,-8) mm, rotated 180°. This is a routing candidate; placement is not a fabrication-approved layout.

Capture verifies that **313 CPU + 144 RAM saved paths** survive actual rendering. It records a source cache snapshot and SHA256, the complete router input and a signal manifest. `unrouted.circuit.json` deliberately contains no new host routes. Zero emitted errors at capture is not evidence of complete routing or power connectivity.

The route command merges shared CPU exits into three-terminal electrical nets, preserves all cached-copper obstacle geometry, and prohibits assignment of existing copper to new nets. `--obstacles-only` omits the redundant preloaded electrical graph, not its physical obstacles. It requests only top/inner2/inner4/inner6 for new signal routing. Independent output validation is still required; the router result alone cannot prove those constraints were obeyed. The parent process imposes a hard diagnostic time limit even if one synchronous solver step hangs.

Initial preloaded-graph attempts exceeded the diagnostic time limit. A subsequent attempt exposed unwanted assignable-via routing; freezing the saved copper resolved that failure mode, after which the first route attempt exhausted its pathing iterations. No complete host copper is accepted yet. New captures remain under `dist/ddr-system/<profile>-<captureHash>/`, with a file-hash provenance manifest. Keep the original circuit, source snapshot, leads and router input from the same capture together; the external RAM source can change independently.

## Remaining physical work

- Complete all host nets with appropriate shared CK/CA topology, termination and point-to-point data lanes.
- Add and physically connect RAM supply/ground, VREF, individual ZQ resistors, VTT and bypass capacitors.
- Match complete CPU + host + RAM electrical delays, not each cache independently.
- Check all emitted copper, pair geometry, 45° bends, layer use and return paths.
- Obtain an actual fabricator stackup and exact CPU speed grade; extract impedance/via delay and validate controller configuration and timing.

The numerical and evidence requirements are implemented in `src/ddr-board-rules.ts` and explained in [the full-board acceptance checklist](real-ddr-acceptance.md). Missing measurements fail closed. The RAM adapter and current source-cache consistency checks are documented in [the memory compatibility audit](ddr-memory-compatibility.md).

## Grouped RAM candidate

```sh
bun scripts/capture-ddr-system.tsx /path/to/mt41k512m8da-107-it-p-fanout bus_grouped
bun scripts/route-ddr-system.ts "$capture_dir" 240 --obstacles-only --pipeline=4 --effort=4 --path-iterations=1000000
```

This capture explicitly uses the six-layer adapter and a 0.1168 mm RAM trace width. The local grouped-RAM copper and rendered shorts checks pass with that width; source files are unchanged. The capture rejects stale grouped caches whose actual byte and CA layers disagree with the expected six-layer roles. The initial full grouped-board routing attempt also reached the router's default pathing-iteration limit; a larger bounded diagnostic is a distinct attempt, not accepted board copper.

## Protected-breakout routing experiment

`prepare-ddr-host-corridors.ts` validates that all captured obstacles, saved routes and actual rendered copper fit inside three solid ten-layer module keepouts. It adds 128 straight outward lead segments, preserving branch aliases and actual exit layers. This avoids asking the host solver to traverse the module's internal fanout. The reduced problem has 131 obstacles instead of 4,905.

```sh
bun scripts/prepare-ddr-host-corridors.ts "$capture_dir"
```

The corridor report and exact leads are stored alongside the capture. A projected planning mode maps the four permitted signal layers to four contiguous solver layers, then maps any result back to the physical ten-layer stack. It is allowed only with the solid enclosing module keepouts. Any new via must still pass full physical ten-layer validation. This does not change the manufactured layer count or reference requirements.

Both the detailed and protected-region routing attempts currently fail the pathing stage. Reversing the two RAM byte placements (`--swap-bytes` on capture) also preserves all 457 cached paths but has not produced an accepted full route. These failed diagnostics do not prove the physical layout impossible. Individual-net isolation established that Pipeline 8 targets preplaced assignable vias and cannot supply the required layer transitions with these immutable caches. Pipeline 4 successfully routes isolated D8, CK and A0 cases with the protected obstacles, but has not completed all 50 nets. A sequential Pipeline 4 attempt produced raw routes for 19 of 50 nets; those routes are not accepted and include angle violations. An older clearance comparison mixed captures after the external RAM changed and must not be used as evidence. No full copper connectivity, timing or SI pass is claimed.

## Angle rule applies to every profile

All four CPU profiles (`native`, `ddr_left`, `ddr_top`, `ddr_bottom`) require turns of at most 45 degrees. Saved escape paths also require horizontal, vertical or 45-degree headings. Fixed support routes now enforce the same headings: 126 formerly off-angle capacitor stubs use 45-degree elbows with unchanged terminals, widths and vias. The refresh command validates all four fixtures before writing and preserves saved escape files byte for byte. Actual rendered copper is checked again during each build. New host routing must pass both heading and joined-exit bend checks before acceptance.

Regenerate support elbows with `bun run generate:fixed-elbows`, then rebuild the profiles. The nine sub-width endpoint legs are entirely covered by their existing pad or via copper (minimum verified coverage margin 0.0265 mm); they are not exposed tiny bends. Full clearance checks still apply after generation.

## Verified partial host copper (2026-09-11)

Capture `dist/ddr-system/bus_grouped-1cd0ca81b895` freezes the current CPU support elbows and RAM source together. Its provenance manifest is verified before routing or physical comparison. `--corridors --prepare-only` on the routing worker produces a four-signal-layer planning input in the same directory; no copied inputs from another capture are required.

The first seven-net raw snapshot has a physically checked partial result under `normalized-seven-net-collars/`. Five host traces connect four complete package-pad nets: DQS0, DQSn0, CKn (both RAM destinations), and DQSn1. All new copper, including exit leads and full-depth via barrels, passes the existing 0.1016 mm clearance and strict heading/join rules; measured minimum new-to-foreign-copper clearance is 0.1208 mm. This is **4/50 connected nets**, not a working DDR interface. In particular, neither complete clock-pair routing nor differential coupling/skew acceptance is established.

The normalizer preserves route terminals, via positions, widths and layers. Shortcut candidates require a complete physical-check predicate. Fixed 0.2 mm outward continuations preserve the published exit direction; rejected candidates remain rejected. The spatially accelerated copper checker was compared with its brute-force implementation on the actual capture and produces an identical report, including the exact clearance minimum and connectivity.

```sh
capture_dir=dist/ddr-system/bus_grouped-1cd0ca81b895
bun scripts/route-ddr-system-worker.ts "$capture_dir" 120 --corridors --obstacles-only --project-signal-layers --prepare-only
bun scripts/normalize-ddr-capture.ts "$capture_dir" "$capture_dir/raw-seven-net-snapshot.json" "$capture_dir/normalized-seven-net-collars"
bun scripts/check-ddr-capture-copper.ts "$capture_dir" "$capture_dir/normalized-seven-net-collars/candidate.physical.json" "$capture_dir/normalized-seven-net-collars/physical-report.json"
```

The last two commands deliberately return a nonzero status while full connectivity remains incomplete. Their reports distinguish passing partial geometry from complete-interface acceptance. RAM power, termination, complete host routing, delay matching and electrical signoff remain required.

The tighter-obstacle sequential pass completed all 47 scheduled groups in 446.835 seconds and produced 8 raw nets / 11 raw traces. After physical normalization, it still yields four complete nets. Most other groups hit their bounded watchdog; this is not proof of physical unroutability. DQM0 illustrates an explicit geometry issue: its left-facing RAM exit must reverse toward the CPU through multiple legal 45-degree turns, rather than the raw router's immediate sharp turn.

The subsequent endpoint-wrap candidate pass improves this to **5/50 complete nets**, adding DQM0. Its seven accepted host traces are under `normalized-tight-wraps/`; all new-copper and joined-angle checks remain clean, with the same 0.1208 mm minimum clearance. It tested bounded 0.2/0.4/0.8 mm turn-around candidates through the full physical predicate, preserving terminals and vias. `physical-report.json` still correctly reports `valid: false` because 45 nets remain disconnected. This supersedes the four-net result only within that older capture; it is not a seed for the current AM3352-specific RAM capture.

## Current AM3352-specific RAM contract

The RAM project now provides full `am3352-byte0` and `am3352-byte1` components. Their data/strobe layers are inner2 and inner4; CA/CK use inner6. Each contains 27 **interior shared-trunk taps**, replacing the older edge-only CA/CK interface. Its local reference pours and stitching are part of the component. The legacy five-net result above belongs to the old adapter capture and must not be used as a seed for this different geometry.

The current imported capture is `dist/ddr-system/host-taps-54af3e346b5e`. It retains 457 saved paths, four local reference pours and 54 interior RAM trunk taps. `import-ddr-host-capture.ts` checks all 78 branch endpoint identities against explicit source ports, checks the current adapted RAM paths against rendered copper, sanitizes inferred port annotations, and reconstructs 6,194 physical obstacles without inheriting stale captured aliases. All 851 current route-point annotations passed identity, position and layer checks. The older solid-module corridor abstraction now explicitly rejects these interior-tap profiles.

The initial, subsequently superseded short DQS pairs were reproduced against this capture and checked again with the independent whole-copper checker, including the actual BREP reference pours and their holes. Four complete nets pass physical connectivity, clearance and joined-angle checks. Host DQS0 length is 11.142858 mm per leg; DQS1 is 10.741097 mm per leg. Each pair's complete planar skew, including both escapes, is 0.099999 mm; host uncoupled length is 0.521665 mm per leg. The pairs use no new vias and have 0.20 mm minimum clearance in the pair audit. These are useful paired corridors, **not complete-byte timing solutions**; they still require tuning to the longest member of their respective byte.

Reproduction uses caller paths and an isolated output directory:

```sh
bun "$ram_dir/scripts/capture-am3352-integration.tsx" "$cpu_dir" "$capture_output"
bun scripts/import-ddr-host-capture.ts "$ram_dir" "$capture_output"
# Use the hash-named directory printed by the importer as $host_capture.
bun "$ram_dir/scripts/route-am3352-trunks-worker.ts" "$host_capture" 60 --prepare-only
bun "$ram_dir/scripts/generate-am3352-dqs-pairs.ts" "$host_capture/forced-trunk-routing-input.json" "$host_capture/unrouted.circuit.json" "$host_capture/dqs-pairs"
```

The shared trunk contract forces CPU → RAM0 tap → RAM1 tap; termination still has to be added. Reference continuity outside the RAMs, all support connections, complete routes, byte tuning and electrical signoff remain unfinished. `check-ddr-capture-copper.ts` now accepts full RAM-component captures and validates emitted polygon pours instead of omitting them.

A bounded shared-trunk attempt on this fresh input reached `portPointPathingSolver` but was stopped by its 63-second external watchdog. No trunk copper from that attempt is accepted. The strobe-pair candidate is independent of that unfinished routing attempt. The capture's local reference pours do not replace a complete shared-board reference and power design.

### Reproducing the host width correction

`bun scripts/standardize-ddr-host-width.ts CAPTURE PHYSICAL_BUNDLE OUTPUT_DIRECTORY` applies 0.12 mm host widths and emits a candidate only after the complete uncropped copper check passes. It records the input bundle SHA256. `data-exact-width-reproduced/` reproduces the accepted seven-net width change; the power-drop candidate continues to pin the original exact-width bundle hash.

### D1 router terminal preservation failure

The targeted D1 single-layer trials used only physical inner2, 0.12 mm traces and explicit planning clearance. They did not produce an accepted new net. Pipeline4 displaced the RAM terminal by approximately 0.182317 mm even after enabling its exposed terminal-ID and endpoint-preservation options. `data-d1-preserved-terminals/00-DDR_D1.result.json` records the requested and emitted coordinates. The new terminal-contract guard rejects displaced or wrong-layer terminals before normalization; the seven-net seed remains unchanged. Coordinate-rounding repair is limited to 0.001 mm and does not conceal this failure. Further work must locate the solver stage that moves the terminal or use a solver path that preserves it.

Validation for this batch: 100 tests passed in the full suite; the subsequently extended terminal/pipeline-options tests also passed, and typecheck passed. These are software and geometric checks, not full DDR acceptance.

### D1 stage diagnosis and existing octilinear search candidate

The subsequent `data-d1-global-terminal-ids` replay fixed terminal drift by restoring authoritative `pcb_port_id` metadata immediately before GlobalDrc, only where the existing endpoint already matches its declared XY/layer within 0.001 mm. No coordinates are moved by this repair. The final terminal guard passed. Stage provenance showed IDs absent in the high-density output even though its terminal coordinates were correct; final repair had therefore treated those terminals as movable. This supersedes the unresolved terminal-drift diagnosis above. D1 still did not pass the complete geometric acceptance check, and the accepted seed remains seven nets.

`data-d1-stage-copper/report.json` and its individual stage JSON files preserve the exact high-density geometry and independent full-capture checks from a bounded replay. Before high-density force improvement: 20 non-octilinear headings and 9 clearance violations. After stitching: 21 bad headings and 4 clearance violations. After simplification: 10 bad headings and 3 clearance violations. After GlobalDrc: 19 bad headings and 5 clearance violations. Thus no saved stage is a valid 45-degree route; final repair is not the first source of arbitrary angles. Fragment-stage terminal-contract failures additionally include internal mesh endpoints, so they are not evidence that declared terminals moved.

Primary installed source confirms that `SingleHighDensityRouteSolver.handleSimpleCases()` returns a direct segment between arbitrary points. Its eight-neighbor search also clamps grid steps at bounds and appends the exact goal, without a strict all-segment octilinear guarantee. No exposed Pipeline4 angular-grid switch found in this audit fixes these behaviors or constrains later force-based repair.

A concrete next candidate is the already installed `@tscircuit/fanout-solver/lib/route-via-minimal-winding.ts` implementation, using `routeViaMinimalWindingAlternativesSteps(params, 1)` for bounded incremental execution. Its directed grid only permits neighboring headings differing by at most 45 degrees; completed paths are checked for axis/45-degree segments, proper self-crossing and exact segment clearance against obstacles and accepted copper. Suggested initial D1 configuration: `targetLayer: 'inner2'`, `allowSourceLayerRouting: true`, `traceWidth: 0.12`, `clearance: 0.1016`, `gridStep: 0.1`, `maximumRouteOrderAttempts: 1`, `maximumSearchStates: 100000`, `heuristicWeight: 1.2`, and one exact terminal pair. Supply the actual source point as the path start (`viaPoint`) so this same-layer case adds no via; preserve all existing copper in `srj`/`acceptedPlans`. Construct the required `PreparedBus` and source-obstacle identity from the real capture, rather than inventing source copper or moving a terminal. This is an existing deep-module API, not a package-root export, so package-version compatibility must be checked.

This is a recommendation, not an executed routing result. Endpoint connector joins still need the existing strict bend and physical checks: the grid constrains incoming directions, while start/end connector joins are a separate risk. Source-exit tangents must remain correct; `sourceEscapePaths` can represent an authorized fixed continuation. All-ten-layer physical validation, actual endpoint contracts, byte lengths, return paths and power acceptance remain mandatory. The winding-breakout-point solver itself only places boundary points; it is not an obstacle-aware host router. The installed KRT WASM alternative documents grid routing but does not establish the same exact-terminal and maximum-45-degree-turn guarantee, so it is a weaker next choice for this specific failure.

### Existing winding API: eight physically connected nets

The recommended existing winding solver was then exercised once by `scripts/route-ddr-winding.ts`, using the immutable seven-net `data-d4-tuned` seed. It accepted D1 in 1.694 seconds without a normalization pass. The result is `data-d1-winding/candidate.physical.json`: eight connected nets, zero full-capture clearance violations, zero non-45-degree segments or excessive turns, and zero bad joins into fixed copper. The minimum reported new-copper clearance is 0.110 mm. The same original 64 × 42 mm board bounds remain in use; the independent audit reports no board-boundary violation. The preview `data-d1-winding/progress.png` shows the actual saved fanouts and accepted host copper.

The adapter uses all 7,654 conservatively projected signal obstacles mapped back to their physical layer names, full-depth via footprints, and the exact seed trace copper. It verifies the seed against the original ten-layer capture first. D1 uses inner2 only, 0.12 mm width, 0.1016 mm clearance, a 0.1 mm directed grid, one route ordering, a 100,000-state search budget, and a 60-second external watchdog. The actual RAM exit tangent supplies a 0.2 mm fixed continuation that independently passes the physical predicate. The existing generator then searches from that continuation to the exact CPU terminal. The final endpoint contract, strict angle/join check, connectivity, and complete uncropped physical check all pass. No new via was added for D1.

The external RAM project's independent graph audit resolves all eight complete paths. Full planar lengths, including both saved fanouts, are: DQS0_P 34.013315 mm, DQS0_N 34.113314 mm, D0 25.211467 mm, D1 37.172344 mm, D4 34.063315 mm, DM1 31.141674 mm, DQS1_P 31.091675 mm and DQS1_N 31.191674 mm. D1's new host portion is 27.288467 mm. D1 is approximately 3.109030 mm longer than its strobe mean, so this is geometric progress, not byte timing acceptance. D0 still has its previously identified unnecessary top-layer detour and is too short relative to its strobe pair. Shared trunks, remaining data, full timing and electrical signoff remain incomplete. The overall independent audit correctly remains failing; missing-path skew summaries are unproven rather than numerical measurements.

The latest [evidence manifest](../dist/ddr-twenty-one-power59-current/current-evidence-manifest.json) binds the finalized report, current byte budgets, both contracts/caches and power/reference audits. The [current cache-envelope audit](../dist/ddr-twenty-one-power59-current/cache-envelope-audit.json) includes the prepared D15 exit and verifies trace-width/via-radius bounds with zero growth on all sides. The portable wrapper is regenerated from this exact candidate; stale data-signal caches are rejected rather than classified as power overrides.

The read-only [D13 CPU layer assessment](../dist/ddr-d13-cpu-layer-swap-assessment/report.json) identifies CPU D5’s inner6 segment interior at y=−2 as the missing lower fence around D13’s via. A coordinated D11/D13 layer reassignment is a proposed next solver experiment, not accepted copper.

## Isolated D11/D13/D15 routing experiment

The CPU D11/D13 retained-via escape swap is not part of the accepted board. D13 reaches 26.711621 mm in `dist/ddr-d13-collar-codesign-connected`, with D15's actual 0.2 mm outgoing collar reserved and checked. This partial candidate has explicitly retired D11 and D15 hosts. D15's lower transition at (0.3, −2.4) mm passes local clearance, but continuation reached 300,000 states without a route. D11's proposed inner4 exit is fenced by DQS1 geometry: a clear RAM-side landing at (−4.7, 2.3) mm has no CPU prefix after exhausting 283 reachable states. The alternative inner2 CPU escape also fails: the retained barrel at (5.6, −0.8) mm requires ±0.381 mm centerline bypass while adjacent tracks allow only ±0.2476 mm; the search exhausted 85,341 states. These are bounded unsuccessful experiments, not evidence that DDR routing is impossible. Canonical CPU profiles and the accepted 21-signal board retain their prior CPU escapes.

## Directed shared-bus routing order

The current `trunk-direction-audit.json` derives memory-branch tangents from all 54 actual source-owned saved taps, on inner6. It checks the direction driven from the CPU separately from the continuation toward the next RAM or termination. This is stricter than treating any ray of a Y junction as the incoming ray: both CPU-driven paths must turn by at most 45°.

Two planning contracts in `dist/ddr-trunk-order-variants` retain the current physical endpoints and explicitly order CPU → RAM0 → RAM1 or CPU → RAM1 → RAM0. A straight northbound segment has compatible local junction directions at both taps for only 1 of 27 shared signals; the southbound order has 15 of 27. These counts establish local direction feasibility only, not clearance or routability. The remaining signals require turns near the taps or revised local escapes. In particular the inherited CK_P and CK_N branch tangents face opposite vertical directions: reversing RAM order alone does not establish a compliant parallel clock pair. Termination after the last RAM remains unimplemented. Neither planning contract changes accepted copper or qualifies an interface.

## Current bounded feasibility results

`dist/ddr-d13-boundary-feasibility/report.json` proves that retaining the original RAM DQ5 exit gives a 29.614252 mm octilinear lower bound through the retained CPU launch, above the 27.3001 mm budget regardless of CPU boundary choice. Even with the shorter right-facing RAM escape, the best top and bottom CPU boundary bounds are 34.773890 mm and 36.346852 mm; extra outward padding cannot fix this. The attempted inner4 point (2.69, −2) mm is already the M2 exit. A coordinated local layout change is required; these bounds do not prove D13 unroutable.

The first RAM0 E9/F8 repair experiment in `dist/ddr-ram0-e9-dm0-middle` is rejected: its DM0 detour exceeds the matched length and joins the retained suffix at 90°. Its geometry review identifies a 0.0196 mm centerline passage missed by the initial 0.1 mm grid phase, so the failed discrete search is not a proof that the passage is physically closed. RAM0 D1's first coupled power trial also pinches DQ2 between the C1 barrel, strobe tails and DQ6; a static barrel clearance pass alone is insufficient to reserve the data route.

The follow-up `dist/ddr-ram0-e9-dm0-aligned` samples that measured passage with an aligned grid and enforces a safe suffix approach. It exhausts 59,300 states without a route; no new DM0 or power copper is accepted.

The coupled DQ2/DQ6 RAM0 trial finds DQ2 with the old DQ6 tail explicitly pending, but cannot restore DQ6: 59,407 states on the first grid, then 246,570 states on the 0.01 mm refinement with the exact DQ2 proposal retained. Both searches exhaust their reachable frontier without a complete candidate (`dist/ddr-ram0-dq2-dq6-power-fine/report.json`). No byte0 length or accepted power count changes. Further progress requires a different coupled layout or landing, rather than acceptance of the partial DQ2 route.