0hmX/am3352
This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.
- Version
- 1.0.5
- License
- unset
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- 0
docs/signal-exits.md
# Saved signal exit contract
Generated by `bun scripts/document-exits.ts` directly from saved trace paths and the AM3352 ball map. Regenerate after changing any profile. Requested solver exit preferences are not used as evidence of actual exits.
Coordinates and lengths are millimeters in the module-local PCB frame: origin at chip center, +X right, +Y up. The boundary is the profile fanout size listed below, not the 15 × 15 mm package body or the host board edge. “Top side” means +Y boundary; “top layer” means outer copper. These are independent.
Outward direction is the boundary normal toward the host board. Final tangent is the final nonzero copper segment, oriented from the source ball toward the exit. Source escape is the first nonzero segment away from the ball. The final tangent can differ from the outward direction; host routing must meet the actual endpoint/layer and respect approach clearance. None of these directions specifies electrical input/output direction.
Planar length includes all saved XY copper segments from ball center to exit. It excludes package delay, vertical via length, and downstream host copper. Logical via spans describe the connected signal layers only. Every physical via barrel spans all copper layers of its profile, from top through every inner layer to bottom; a logical top→inner2 transition is not a blind via. Unused barrel sections can affect DDR signal integrity.
The JSON contract also records per-layer planar lengths and logical via XY coordinates. Exit metadata is a geometric integration contract, not proof of DDR timing, impedance, reference-plane continuity, or full memory connectivity.
All CPU profiles use only horizontal, vertical and 45° diagonal saved segments in this local frame. Same-layer bends change direction by at most 45° (135° inside corner), including fixed support copper. Fixed capacitor-to-via routes use the same permitted headings. A 90° directional turn must use two separated 45° bends. Rotating the whole module preserves bend angles while rotating segment headings; host continuation routing must enforce its own bend rule.
Run `bun run check:angles` after rebuilding profiles. It checks every saved and fixed path, then all rendered traces (including the 201 edge contacts per profile), with octilinear headings and maximum 45° turns. The rendered audit also checks cross-trace and interior junctions: Y splits must admit a valid incoming direction; T/X or sharp joins fail. Only a coincident same-net via terminates a planar run. The public profile registry drives rendered coverage, so a new profile cannot silently omit this check.
## Placement API
```ts
import { getAM3352Exits, transformAM3352Exit } from '@tsci/0hmX.am3352'
const localExits = getAM3352Exits('native')
const placedExits = localExits.map(exit => transformAM3352Exit(exit, {
pcbX: 25, pcbY: 10, pcbRotation: 90,
}))
```
The public pcbX/pcbY placement remains the CPU center even when the boundary has unequal side padding. getAM3352Bounds(profile) returns the actual CPU-centered min/max bounds; fanoutWidthMm/fanoutHeightMm and padding.left/right/top/bottom give dimensions. Legacy fanoutSizeMm/paddingMm are maximum dimensions only and must not be used to infer symmetric bounds. Transform uses counterclockwise degrees in PCB XY, then translation. Exit coordinates, via coordinates and all three direction vectors transform. Copper layers, lengths and the `side` label remain in the local profile frame; use transformed `outwardDirection` to determine the world-facing side, including non-cardinal rotations. Apply a transform to a fresh local exit, not repeatedly to an already placed result. No layer mirroring is supported.
## native
17 × 17 mm local boundary, x=[-8.5, 8.5], y=[-8.5, 8.5]. Package padding (left/right/top/bottom): 1/1/1/1 mm; 6 layers (top → inner1 → inner2 → inner3 → inner4 → bottom). 201 external signal exits. Fixed local supply and capacitor routes do not terminate at the fanout boundary and are excluded.
### DDR exit distribution
| Side | Copper layer | Signals |
| --- | --- | --- |
| left | top | DDR_A5, DDR_A9, DDR_BA1, DDR_CASn, DDR_ODT, DDR_A1, DDR_D8, DDR_D9, DDR_D15, DDR_D2 |
| left | inner2 | DDR_WEn, DDR_A4, DDR_CKn, DDR_CK, DDR_A7, DDR_A11, DDR_RESETn, DDR_CSn0, DDR_DQM1, DDR_D10, DDR_DQS1, DDR_DQSn1, DDR_DQM0, DDR_D3, DDR_DQS0, DDR_DQSn0 |
| top | inner2 | DDR_BA2 |
| left | inner3 | DDR_A3, DDR_A15, DDR_A12, DDR_A0, DDR_CKE, DDR_A13, DDR_VTP, DDR_D11, DDR_D13, DDR_D0, DDR_D4, DDR_D6 |
| top | inner3 | DDR_BA0 |
| top | inner4 | DDR_A8, DDR_A6 |
| left | inner4 | DDR_A2, DDR_A10, DDR_RASn, DDR_A14, DDR_VREF, DDR_D12, DDR_D14, DDR_D1, DDR_D5, DDR_D7 |
### All signal exits
| Signal | Ball | Side | Outward (dx, dy) | Final tangent (dx, dy) | Source escape (dx, dy) | Layer | Exit (x, y) mm | Planar mm | Logical vias |
| --- | --- | --- | --- | --- | --- | --- | --- | ---: | --- |
| RTC_XTALOUT | A4 | top | (0, 1) | (0, 1) | (0, 1) | top | (-4.4, 8.5) | 1.7 | none |
| RTC_XTALIN | A6 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2.8, 8.5) | 1.7 | none |
| AIN3 | A7 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2, 8.5) | 1.7 | none |
| AIN6 | A8 | top | (0, 1) | (0, 1) | (0, 1) | top | (-1.2, 8.5) | 1.7 | none |
| VREFN | A9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.4, 8.5) | 1.7 | none |
| WARMRSTn | A10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.4, 8.5) | 1.7 | none |
| TDO | A11 | top | (0, 1) | (0, 1) | (0, 1) | top | (1.2, 8.5) | 1.7 | none |
| TCK | A12 | top | (0, 1) | (0, 1) | (0, 1) | top | (2, 8.5) | 1.7 | none |
| MCASP0_ACLKX | A13 | top | (0, 1) | (0, 1) | (0, 1) | top | (2.8, 8.5) | 1.7 | none |
| MCASP0_AHCLKX | A14 | top | (0, 1) | (0, 1) | (0, 1) | top | (3.6, 8.5) | 1.7 | none |
| XDMA_EVENT_INTR0 | A15 | top | (0, 1) | (0, 1) | (0, 1) | top | (4.4, 8.5) | 1.7 | none |
| SPI0_CS0 | A16 | top | (0, 1) | (0, 1) | (0, 1) | top | (5.2, 8.5) | 1.7 | none |
| SPI0_SCLK | A17 | top | (0, 1) | (0, 1) | (0, 1) | top | (6, 8.5) | 1.7 | none |
| DDR_A5 | B1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, 6) | 1.7 | none |
| DDR_WEn | B2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 6) | 2.877367 | top→inner2 |
| DDR_BA2 | B3 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-5.2, 8.5) | 2.877367 | top→inner2 |
| RTC_PWRONRSTn | B5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-3.6, 8.5) | 2.877367 | top→inner2 |
| AIN0 | B6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2.8, 8.5) | 2.877367 | top→inner2 |
| AIN2 | B7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2, 8.5) | 2.877367 | top→inner2 |
| AIN5 | B8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-1.2, 8.5) | 2.877367 | top→inner2 |
| VREFP | B9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.07874, 8.5) | 2.63307 | none |
| TRSTn | B10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.72126, 8.5) | 2.63307 | none |
| TDI | B11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (1.2, 8.5) | 2.877367 | top→inner2 |
| MCASP0_ACLKR | B12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2, 8.5) | 2.877367 | top→inner2 |
| MCASP0_FSX | B13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2.8, 8.5) | 2.877367 | top→inner2 |
| EMU1 | B14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (3.6, 8.5) | 2.877367 | top→inner2 |
| PWRONRSTn | B15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (4.4, 8.5) | 2.877367 | top→inner2 |
| SPI0_D1 | B16 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (5.2, 8.5) | 2.877367 | top→inner2 |
| SPI0_D0 | B17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 6) | 2.877367 | top→inner2 |
| EXTINTn | B18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 6) | 1.7 | none |
| DDR_A9 | C1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, 5.2) | 1.7 | none |
| DDR_A4 | C2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 5.2) | 2.877367 | top→inner2 |
| DDR_A3 | C3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, 5.2) | 3.677367 | top→inner3 |
| DDR_BA0 | C4 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner3 | (-4.4, 8.5) | 3.677367 | top→inner3 |
| EXT_WAKEUP | C5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner3 | (-3.6, 8.5) | 3.677367 | top→inner3 |
| PMIC_POWER_EN | C6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner3 | (-2.8, 8.5) | 3.677367 | top→inner3 |
| AIN1 | C7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner3 | (-2, 8.5) | 3.677367 | top→inner3 |
| AIN4 | C8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner3 | (-1.2, 8.5) | 3.677367 | top→inner3 |
| AIN7 | C9 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner3 | (-0.4, 8.5) | 3.677367 | top→inner3 |
| TMS | C11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner3 | (1.2, 8.5) | 3.677367 | top→inner3 |
| MCASP0_AHCLKR | C12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner3 | (2, 8.5) | 3.677367 | top→inner3 |
| MCASP0_FSR | C13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner3 | (2.8, 8.5) | 3.677367 | top→inner3 |
| EMU0 | C14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner3 | (3.6, 8.5) | 3.677367 | top→inner3 |
| SPI0_CS1 | C15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner3 | (4.4, 8.5) | 3.677367 | top→inner3 |
| I2C0_SCL | C16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner3 | (8.5, 5.2) | 3.677367 | top→inner3 |
| I2C0_SDA | C17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 5.2) | 2.877367 | top→inner2 |
| ECAP0_IN_PWM0_OUT | C18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 5.2) | 1.7 | none |
| DDR_CKn | D1 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 4.4) | 3.098628 | top→inner2 |
| DDR_CK | D2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 4.72126) | 3.198627 | top→inner2 |
| DDR_A15 | D3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, 4.4) | 3.677367 | top→inner3 |
| DDR_A8 | D4 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-4.4, 8.5) | 4.477367 | top→inner4 |
| DDR_A6 | D5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-3.6, 8.5) | 4.477367 | top→inner4 |
| MCASP0_AXR0 | D12 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (2, 8.5) | 4.477367 | top→inner4 |
| MCASP0_AXR1 | D13 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (2.8, 8.5) | 4.477367 | top→inner4 |
| XDMA_EVENT_INTR1 | D14 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (3.6, 8.5) | 4.477367 | top→inner4 |
| UART1_TXD | D15 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (4.4, 8.5) | 4.477367 | top→inner4 |
| UART1_RXD | D16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner3 | (8.5, 4.4) | 3.677367 | top→inner3 |
| UART1_RTSn | D17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 4.4) | 2.877367 | top→inner2 |
| UART1_CTSn | D18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 4.4) | 1.7 | none |
| DDR_BA1 | E1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, 3.6) | 1.7 | none |
| DDR_A7 | E2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 3.6) | 2.877367 | top→inner2 |
| DDR_A12 | E3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, 3.6) | 3.677367 | top→inner3 |
| DDR_A2 | E4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, 3.6) | 4.477367 | top→inner4 |
| UART0_RXD | E15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.5, 3.6) | 4.477367 | top→inner4 |
| UART0_TXD | E16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner3 | (8.5, 3.6) | 3.677367 | top→inner3 |
| UART0_RTSn | E17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 3.6) | 2.877367 | top→inner2 |
| UART0_CTSn | E18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 3.6) | 1.7 | none |
| DDR_CASn | F1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, 2.8) | 1.7 | none |
| DDR_A11 | F2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 2.8) | 2.877367 | top→inner2 |
| DDR_A0 | F3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, 2.8) | 3.677367 | top→inner3 |
| DDR_A10 | F4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, 2.8) | 4.477367 | top→inner4 |
| USB1_DRVVBUS | F15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.5, 2.8) | 4.477367 | top→inner4 |
| USB0_DRVVBUS | F16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner3 | (8.5, 2.8) | 3.677367 | top→inner3 |
| MMC0_DAT3 | F17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 2.8) | 2.877367 | top→inner2 |
| MMC0_DAT2 | F18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 2.8) | 1.7 | none |
| DDR_ODT | G1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, 2) | 1.7 | none |
| DDR_RESETn | G2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 2) | 2.877367 | top→inner2 |
| DDR_CKE | G3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, 2) | 3.677367 | top→inner3 |
| DDR_RASn | G4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, 2) | 4.477367 | top→inner4 |
| MMC0_DAT1 | G15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.5, 2) | 4.477367 | top→inner4 |
| MMC0_DAT0 | G16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner3 | (8.5, 2) | 3.677367 | top→inner3 |
| MMC0_CLK | G17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 2) | 2.877367 | top→inner2 |
| MMC0_CMD | G18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 2) | 1.7 | none |
| DDR_A1 | H1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, 1.2) | 1.7 | none |
| DDR_CSn0 | H2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 1.2) | 2.877367 | top→inner2 |
| DDR_A13 | H3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, 1.2) | 3.677367 | top→inner3 |
| DDR_A14 | H4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, 1.2) | 4.477367 | top→inner4 |
| MII1_COL | H16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner3 | (8.5, 1.2) | 3.677367 | top→inner3 |
| MII1_CRS | H17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 1.2) | 2.877367 | top→inner2 |
| RMII1_REF_CLK | H18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 1.2) | 1.7 | none |
| DDR_D8 | J1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, 0.4) | 1.7 | none |
| DDR_DQM1 | J2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, 0.4) | 2.877367 | top→inner2 |
| DDR_VTP | J3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, 0.4) | 3.677367 | top→inner3 |
| DDR_VREF | J4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, 0.4) | 4.477367 | top→inner4 |
| MII1_RX_ER | J15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.5, 0.4) | 4.477367 | top→inner4 |
| MII1_TX_EN | J16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner3 | (8.5, 0.4) | 3.677367 | top→inner3 |
| MII1_RX_DV | J17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, 0.4) | 2.877367 | top→inner2 |
| MII1_TXD3 | J18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, 0.4) | 1.7 | none |
| DDR_D9 | K1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, -0.4) | 1.7 | none |
| DDR_D10 | K2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -0.4) | 2.877367 | top→inner2 |
| DDR_D11 | K3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, -0.4) | 3.677367 | top→inner3 |
| DDR_D12 | K4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, -0.4) | 4.477367 | top→inner4 |
| MII1_TXD2 | K15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.5, -0.4) | 4.477367 | top→inner4 |
| MII1_TXD1 | K16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner3 | (8.5, -0.4) | 3.677367 | top→inner3 |
| MII1_TXD0 | K17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -0.4) | 2.877367 | top→inner2 |
| MII1_TX_CLK | K18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, -0.4) | 1.7 | none |
| DDR_DQS1 | L1 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -1.2) | 3.098628 | top→inner2 |
| DDR_DQSn1 | L2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -0.87874) | 3.198627 | top→inner2 |
| DDR_D13 | L3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, -1.2) | 3.677367 | top→inner3 |
| DDR_D14 | L4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, -1.2) | 4.477367 | top→inner4 |
| MII1_RXD1 | L15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.5, -1.2) | 4.477367 | top→inner4 |
| MII1_RXD2 | L16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner3 | (8.5, -1.2) | 3.677367 | top→inner3 |
| MII1_RXD3 | L17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -1.2) | 2.877367 | top→inner2 |
| MII1_RX_CLK | L18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, -1.2) | 1.7 | none |
| DDR_D15 | M1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, -2) | 1.7 | none |
| DDR_DQM0 | M2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -2) | 2.877367 | top→inner2 |
| DDR_D0 | M3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, -2) | 3.677367 | top→inner3 |
| DDR_D1 | M4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, -2) | 4.477367 | top→inner4 |
| USB0_CE | M15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.5, -2) | 4.477367 | top→inner4 |
| MII1_RXD0 | M16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner3 | (8.5, -2) | 3.677367 | top→inner3 |
| MDIO | M17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -2) | 2.877367 | top→inner2 |
| MDC | M18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, -2) | 1.7 | none |
| DDR_D2 | N1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, -2.8) | 1.7 | none |
| DDR_D3 | N2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -2.8) | 2.877367 | top→inner2 |
| DDR_D4 | N3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, -2.8) | 3.677367 | top→inner3 |
| DDR_D5 | N4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, -2.8) | 4.477367 | top→inner4 |
| USB0_DP | N17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -2.47874) | 3.198627 | top→inner2 |
| USB0_DM | N18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -2.8) | 3.098628 | top→inner2 |
| DDR_DQS0 | P1 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -3.6) | 3.098628 | top→inner2 |
| DDR_DQSn0 | P2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -3.27874) | 3.198627 | top→inner2 |
| DDR_D6 | P3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, -3.6) | 3.677367 | top→inner3 |
| DDR_D7 | P4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, -3.6) | 4.477367 | top→inner4 |
| USB0_VBUS | P15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.5, -3.6) | 4.477367 | top→inner4 |
| USB0_ID | P16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner3 | (8.5, -3.6) | 3.677367 | top→inner3 |
| USB1_ID | P17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -3.6) | 2.877367 | top→inner2 |
| USB1_CE | P18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, -3.6) | 1.7 | none |
| LCD_DATA0 | R1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, -4.4) | 1.7 | none |
| LCD_DATA1 | R2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -4.4) | 2.877367 | top→inner2 |
| LCD_DATA2 | R3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner3 | (-8.5, -4.4) | 3.677367 | top→inner3 |
| LCD_DATA3 | R4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-8.5, -4.4) | 4.477367 | top→inner4 |
| LCD_HSYNC | R5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-3.6, -8.5) | 4.477367 | top→inner4 |
| LCD_AC_BIAS_EN | R6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2.8, -8.5) | 4.477367 | top→inner4 |
| GPMC_ADVn_ALE | R7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2, -8.5) | 4.477367 | top→inner4 |
| GPMC_AD2 | R8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-1.2, -8.5) | 4.477367 | top→inner4 |
| GPMC_AD6 | R9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-0.4, -8.5) | 4.477367 | top→inner4 |
| GPMC_AD13 | R12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2, -8.5) | 4.477367 | top→inner4 |
| GPMC_A0 | R13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2.8, -8.5) | 4.477367 | top→inner4 |
| GPMC_A4 | R14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (3.6, -8.5) | 4.477367 | top→inner4 |
| USB1_DP | R17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -4.07874) | 3.198627 | top→inner2 |
| USB1_DM | R18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -4.4) | 3.098628 | top→inner2 |
| LCD_DATA4 | T1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, -5.2) | 1.7 | none |
| LCD_DATA5 | T2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -5.2) | 2.877367 | top→inner2 |
| LCD_DATA6 | T3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (-5.2, -8.5) | 3.677367 | top→inner3 |
| LCD_DATA7 | T4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (-4.4, -8.5) | 3.677367 | top→inner3 |
| LCD_DATA15 | T5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (-3.6, -8.5) | 3.677367 | top→inner3 |
| GPMC_BEn0_CLE | T6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (-2.8, -8.5) | 3.677367 | top→inner3 |
| GPMC_OEn_REn | T7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (-2, -8.5) | 3.677367 | top→inner3 |
| GPMC_AD3 | T8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (-1.2, -8.5) | 3.677367 | top→inner3 |
| GPMC_AD7 | T9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (-0.4, -8.5) | 3.677367 | top→inner3 |
| GPMC_AD9 | T10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (0.4, -8.5) | 3.677367 | top→inner3 |
| GPMC_AD10 | T11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (1.2, -8.5) | 3.677367 | top→inner3 |
| GPMC_AD12 | T12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (2, -8.5) | 3.677367 | top→inner3 |
| GPMC_CSn3 | T13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (2.8, -8.5) | 3.677367 | top→inner3 |
| GPMC_A3 | T14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (3.6, -8.5) | 3.677367 | top→inner3 |
| GPMC_A7 | T15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (4.4, -8.5) | 3.677367 | top→inner3 |
| GPMC_A10 | T16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner3 | (5.2, -8.5) | 3.677367 | top→inner3 |
| GPMC_WAIT0 | T17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.5, -5.2) | 2.877367 | top→inner2 |
| USB1_VBUS | T18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, -5.2) | 1.7 | none |
| LCD_DATA8 | U1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-8.5, -6) | 1.7 | none |
| LCD_DATA9 | U2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-8.5, -6) | 2.877367 | top→inner2 |
| LCD_DATA10 | U3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-5.2, -8.5) | 2.877367 | top→inner2 |
| LCD_DATA11 | U4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-4.4, -8.5) | 2.877367 | top→inner2 |
| LCD_VSYNC | U5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-3.6, -8.5) | 2.877367 | top→inner2 |
| GPMC_WEn | U6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2.8, -8.5) | 2.877367 | top→inner2 |
| GPMC_AD0 | U7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2, -8.5) | 2.877367 | top→inner2 |
| GPMC_AD4 | U8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-1.2, -8.5) | 2.877367 | top→inner2 |
| GPMC_CSn1 | U9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-0.4, -8.5) | 2.877367 | top→inner2 |
| GPMC_AD8 | U10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (0.4, -8.5) | 2.877367 | top→inner2 |
| XTALOUT | U11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (1.2, -8.5) | 2.877367 | top→inner2 |
| GPMC_AD11 | U12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2, -8.5) | 2.877367 | top→inner2 |
| GPMC_AD15 | U13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2.8, -8.5) | 2.877367 | top→inner2 |
| GPMC_A2 | U14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (3.6, -8.5) | 2.877367 | top→inner2 |
| GPMC_A6 | U15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (4.4, -8.5) | 2.877367 | top→inner2 |
| GPMC_A9 | U16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (5.2, -8.5) | 2.877367 | top→inner2 |
| GPMC_WPn | U17 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (6, -8.5) | 2.877367 | top→inner2 |
| GPMC_BEn1 | U18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.5, -6) | 1.7 | none |
| LCD_DATA12 | V2 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-6, -8.5) | 1.7 | none |
| LCD_DATA13 | V3 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-5.2, -8.5) | 1.7 | none |
| LCD_DATA14 | V4 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-4.4, -8.5) | 1.7 | none |
| LCD_PCLK | V5 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-3.6, -8.5) | 1.7 | none |
| GPMC_CSn0 | V6 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2.8, -8.5) | 1.7 | none |
| GPMC_AD1 | V7 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2, -8.5) | 1.7 | none |
| GPMC_AD5 | V8 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-1.2, -8.5) | 1.7 | none |
| GPMC_CSn2 | V9 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-0.4, -8.5) | 1.7 | none |
| XTALIN | V10 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (0.4, -8.5) | 1.7 | none |
| GPMC_CLK | V12 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2, -8.5) | 1.7 | none |
| GPMC_AD14 | V13 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2.8, -8.5) | 1.7 | none |
| GPMC_A1 | V14 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (3.6, -8.5) | 1.7 | none |
| GPMC_A5 | V15 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (4.4, -8.5) | 1.7 | none |
| GPMC_A8 | V16 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (5.2, -8.5) | 1.7 | none |
| GPMC_A11 | V17 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (6, -8.5) | 1.7 | none |
## ddr_left
17.78 × 17.74 mm local boundary, x=[-9.31, 8.47], y=[-8.38, 9.36]. Package padding (left/right/top/bottom): 1.81/0.97/1.86/0.88 mm; 10 layers (top → inner1 → inner2 → inner3 → inner4 → inner5 → inner6 → inner7 → inner8 → bottom). 201 external signal exits. Fixed local supply and capacitor routes do not terminate at the fanout boundary and are excluded.
### DDR exit distribution
| Side | Copper layer | Signals |
| --- | --- | --- |
| left | top | DDR_A5, DDR_A9, DDR_BA1, DDR_CASn, DDR_ODT, DDR_A1, DDR_D8, DDR_D9, DDR_D15, DDR_D2 |
| left | inner2 | DDR_WEn, DDR_A3, DDR_BA0, DDR_A11, DDR_A0, DDR_A10, DDR_DQM1, DDR_VTP, DDR_VREF, DDR_D0, DDR_D1, DDR_D3, DDR_DQS0, DDR_DQSn0 |
| left | inner4 | DDR_BA2, DDR_A7, DDR_A12, DDR_A2, DDR_CSn0, DDR_A13, DDR_A14, DDR_DQS1, DDR_DQSn1, DDR_D13, DDR_D14, DDR_DQM0, DDR_D6, DDR_D7 |
| left | inner6 | DDR_A4, DDR_CKn, DDR_CK, DDR_A15, DDR_A8, DDR_A6, DDR_RESETn, DDR_CKE, DDR_RASn, DDR_D10, DDR_D11, DDR_D12, DDR_D4, DDR_D5 |
### All signal exits
| Signal | Ball | Side | Outward (dx, dy) | Final tangent (dx, dy) | Source escape (dx, dy) | Layer | Exit (x, y) mm | Planar mm | Logical vias |
| --- | --- | --- | --- | --- | --- | --- | --- | ---: | --- |
| RTC_XTALOUT | A4 | top | (0, 1) | (0, 1) | (0, 1) | top | (-4.4, 9.36) | 2.56 | none |
| RTC_XTALIN | A6 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2.8, 9.36) | 2.56 | none |
| AIN3 | A7 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2, 9.36) | 2.56 | none |
| AIN6 | A8 | top | (0, 1) | (0, 1) | (0, 1) | top | (-1.2, 9.36) | 2.56 | none |
| VREFN | A9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.4, 9.36) | 2.56 | none |
| WARMRSTn | A10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.4, 9.36) | 2.56 | none |
| TDO | A11 | top | (0, 1) | (0, 1) | (0, 1) | top | (1.2, 9.36) | 2.56 | none |
| TCK | A12 | top | (0, 1) | (0, 1) | (0, 1) | top | (2, 9.36) | 2.56 | none |
| MCASP0_ACLKX | A13 | top | (0, 1) | (0, 1) | (0, 1) | top | (2.8, 9.36) | 2.56 | none |
| MCASP0_AHCLKX | A14 | top | (0, 1) | (0, 1) | (0, 1) | top | (3.6, 9.36) | 2.56 | none |
| XDMA_EVENT_INTR0 | A15 | top | (0, 1) | (0, 1) | (0, 1) | top | (4.4, 9.36) | 2.56 | none |
| SPI0_CS0 | A16 | top | (0, 1) | (0, 1) | (0, 1) | top | (5.2, 9.36) | 2.56 | none |
| SPI0_SCLK | A17 | top | (0, 1) | (0, 1) | (0, 1) | top | (6, 9.36) | 2.56 | none |
| DDR_A5 | B1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, 6) | 2.51 | none |
| DDR_WEn | B2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, 6) | 3.646643 | top→inner2 |
| DDR_BA2 | B3 | left | (-1, 0) | (-1, 0) | (-0.707107, 0.707107) | inner4 | (-9.31, 6.8) | 4.446643 | top→inner4 |
| RTC_PWRONRSTn | B5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-3.6, 9.36) | 3.737367 | top→inner2 |
| AIN0 | B6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2.8, 9.36) | 3.737367 | top→inner2 |
| AIN2 | B7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2, 9.36) | 3.737367 | top→inner2 |
| AIN5 | B8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-1.2, 9.36) | 3.737367 | top→inner2 |
| VREFP | B9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.07874, 9.36) | 3.49307 | none |
| TRSTn | B10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.72126, 9.36) | 3.49307 | none |
| TDI | B11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (1.2, 9.36) | 3.737367 | top→inner2 |
| MCASP0_ACLKR | B12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2, 9.36) | 3.737367 | top→inner2 |
| MCASP0_FSX | B13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2.8, 9.36) | 3.737367 | top→inner2 |
| EMU1 | B14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (3.6, 9.36) | 3.737367 | top→inner2 |
| PWRONRSTn | B15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (4.4, 9.36) | 3.737367 | top→inner2 |
| SPI0_D1 | B16 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (5.2, 9.36) | 3.737367 | top→inner2 |
| SPI0_D0 | B17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 6) | 2.847367 | top→inner2 |
| EXTINTn | B18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 6) | 1.67 | none |
| DDR_A9 | C1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, 5.2) | 2.51 | none |
| DDR_A4 | C2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 5.2) | 3.646643 | top→inner6 |
| DDR_A3 | C3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, 5.2) | 4.446643 | top→inner2 |
| DDR_BA0 | C4 | left | (-1, 0) | (-1, 0) | (-0.707107, 0.707107) | inner2 | (-9.31, 6.8) | 6.044768 | top→inner2 |
| EXT_WAKEUP | C5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-3.6, 9.36) | 4.537367 | top→inner4 |
| PMIC_POWER_EN | C6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-2.8, 9.36) | 4.537367 | top→inner4 |
| AIN1 | C7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-2, 9.36) | 4.537367 | top→inner4 |
| AIN4 | C8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-1.2, 9.36) | 4.537367 | top→inner4 |
| AIN7 | C9 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-0.4, 9.36) | 4.537367 | top→inner4 |
| TMS | C11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (1.2, 9.36) | 4.537367 | top→inner4 |
| MCASP0_AHCLKR | C12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (2, 9.36) | 4.537367 | top→inner4 |
| MCASP0_FSR | C13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (2.8, 9.36) | 4.537367 | top→inner4 |
| EMU0 | C14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (3.6, 9.36) | 4.537367 | top→inner4 |
| SPI0_CS1 | C15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (4.4, 9.36) | 4.537367 | top→inner4 |
| I2C0_SCL | C16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 5.2) | 3.647367 | top→inner4 |
| I2C0_SDA | C17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 5.2) | 2.847367 | top→inner2 |
| ECAP0_IN_PWM0_OUT | C18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 5.2) | 1.67 | none |
| DDR_CKn | D1 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 4.4) | 3.944769 | top→inner6 |
| DDR_CK | D2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 4.8) | 4.044768 | top→inner6 |
| DDR_A15 | D3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 3.6) | 4.446643 | top→inner6 |
| DDR_A8 | D4 | left | (-1, 0) | (-1, 0) | (-0.707107, 0.707107) | inner6 | (-9.31, 8.98) | 9.633052 | top→inner6 |
| DDR_A6 | D5 | left | (-1, 0) | (-1, 0) | (-0.707107, 0.707107) | inner6 | (-9.31, 9.2) | 10.607056 | top→inner6 |
| MCASP0_AXR0 | D12 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (2, 9.36) | 5.337367 | top→inner6 |
| MCASP0_AXR1 | D13 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (2.8, 9.36) | 5.337367 | top→inner6 |
| XDMA_EVENT_INTR1 | D14 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (3.6, 9.36) | 5.337367 | top→inner6 |
| UART1_TXD | D15 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (4.4, 9.36) | 5.337367 | top→inner6 |
| UART1_RXD | D16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 4.4) | 3.647367 | top→inner4 |
| UART1_RTSn | D17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 4.4) | 2.847367 | top→inner2 |
| UART1_CTSn | D18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 4.4) | 1.67 | none |
| DDR_BA1 | E1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, 3.6) | 2.51 | none |
| DDR_A7 | E2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, 3.6) | 3.646643 | top→inner4 |
| DDR_A12 | E3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, 4.4) | 5.244768 | top→inner4 |
| DDR_A2 | E4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, 5.2) | 6.844768 | top→inner4 |
| UART0_RXD | E15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 3.6) | 4.447367 | top→inner6 |
| UART0_TXD | E16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 3.6) | 3.647367 | top→inner4 |
| UART0_RTSn | E17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 3.6) | 2.847367 | top→inner2 |
| UART0_CTSn | E18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 3.6) | 1.67 | none |
| DDR_CASn | F1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, 2.8) | 2.51 | none |
| DDR_A11 | F2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, 2.8) | 3.646643 | top→inner2 |
| DDR_A0 | F3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, 3.6) | 5.244768 | top→inner2 |
| DDR_A10 | F4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, 2) | 5.246643 | top→inner2 |
| USB1_DRVVBUS | F15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 2.8) | 4.447367 | top→inner6 |
| USB0_DRVVBUS | F16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 2.8) | 3.647367 | top→inner4 |
| MMC0_DAT3 | F17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 2.8) | 2.847367 | top→inner2 |
| MMC0_DAT2 | F18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 2.8) | 1.67 | none |
| DDR_ODT | G1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, 2) | 2.51 | none |
| DDR_RESETn | G2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 2) | 3.646643 | top→inner6 |
| DDR_CKE | G3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 2.8) | 5.244768 | top→inner6 |
| DDR_RASn | G4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 1.2) | 5.246643 | top→inner6 |
| MMC0_DAT1 | G15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 2) | 4.447367 | top→inner6 |
| MMC0_DAT0 | G16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 2) | 3.647367 | top→inner4 |
| MMC0_CLK | G17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 2) | 2.847367 | top→inner2 |
| MMC0_CMD | G18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 2) | 1.67 | none |
| DDR_A1 | H1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, 1.2) | 2.51 | none |
| DDR_CSn0 | H2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, 1.2) | 3.646643 | top→inner4 |
| DDR_A13 | H3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, 2) | 5.244768 | top→inner4 |
| DDR_A14 | H4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, 2.8) | 6.844768 | top→inner4 |
| MII1_COL | H16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 1.2) | 3.647367 | top→inner4 |
| MII1_CRS | H17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 1.2) | 2.847367 | top→inner2 |
| RMII1_REF_CLK | H18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 1.2) | 1.67 | none |
| DDR_D8 | J1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, 0.4) | 2.51 | none |
| DDR_DQM1 | J2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, 0.4) | 3.646643 | top→inner2 |
| DDR_VTP | J3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, 1.2) | 5.244768 | top→inner2 |
| DDR_VREF | J4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -0.4) | 5.246643 | top→inner2 |
| MII1_RX_ER | J15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, 0.4) | 4.447367 | top→inner6 |
| MII1_TX_EN | J16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, 0.4) | 3.647367 | top→inner4 |
| MII1_RX_DV | J17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 0.4) | 2.847367 | top→inner2 |
| MII1_TXD3 | J18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 0.4) | 1.67 | none |
| DDR_D9 | K1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, -0.4) | 2.51 | none |
| DDR_D10 | K2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, -0.4) | 3.646643 | top→inner6 |
| DDR_D11 | K3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, -1.2) | 4.446643 | top→inner6 |
| DDR_D12 | K4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, 0.4) | 6.044768 | top→inner6 |
| MII1_TXD2 | K15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -0.4) | 4.447367 | top→inner6 |
| MII1_TXD1 | K16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -0.4) | 3.647367 | top→inner4 |
| MII1_TXD0 | K17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -0.4) | 2.847367 | top→inner2 |
| MII1_TX_CLK | K18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -0.4) | 1.67 | none |
| DDR_DQS1 | L1 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, -1.2) | 3.944769 | top→inner4 |
| DDR_DQSn1 | L2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, -0.8) | 4.044768 | top→inner4 |
| DDR_D13 | L3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, -0.4) | 5.244768 | top→inner4 |
| DDR_D14 | L4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, 0.4) | 6.844768 | top→inner4 |
| MII1_RXD1 | L15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -1.2) | 4.447367 | top→inner6 |
| MII1_RXD2 | L16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -1.2) | 3.647367 | top→inner4 |
| MII1_RXD3 | L17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -1.2) | 2.847367 | top→inner2 |
| MII1_RX_CLK | L18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -1.2) | 1.67 | none |
| DDR_D15 | M1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, -2) | 2.51 | none |
| DDR_DQM0 | M2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, -2) | 3.646643 | top→inner4 |
| DDR_D0 | M3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -2) | 4.446643 | top→inner2 |
| DDR_D1 | M4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -1.2) | 6.044768 | top→inner2 |
| USB0_CE | M15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -2) | 4.447367 | top→inner6 |
| MII1_RXD0 | M16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -2) | 3.647367 | top→inner4 |
| MDIO | M17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2) | 2.847367 | top→inner2 |
| MDC | M18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -2) | 1.67 | none |
| DDR_D2 | N1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, -2.8) | 2.51 | none |
| DDR_D3 | N2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -2.8) | 3.646643 | top→inner2 |
| DDR_D4 | N3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, -2.8) | 4.446643 | top→inner6 |
| DDR_D5 | N4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, -3.6) | 5.246643 | top→inner6 |
| USB0_DP | N17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2.47874) | 3.168627 | top→inner2 |
| USB0_DM | N18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2.8) | 3.068628 | top→inner2 |
| DDR_DQS0 | P1 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -3.6) | 3.944769 | top→inner2 |
| DDR_DQSn0 | P2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -3.2) | 4.044768 | top→inner2 |
| DDR_D6 | P3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, -3.6) | 4.446643 | top→inner4 |
| DDR_D7 | P4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, -2.8) | 6.044768 | top→inner4 |
| USB0_VBUS | P15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -3.6) | 4.447367 | top→inner6 |
| USB0_ID | P16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -3.6) | 3.647367 | top→inner4 |
| USB1_ID | P17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -3.6) | 2.847367 | top→inner2 |
| USB1_CE | P18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -3.6) | 1.67 | none |
| LCD_DATA0 | R1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, -4.4) | 2.51 | none |
| LCD_DATA1 | R2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -4.4) | 3.687367 | top→inner2 |
| LCD_DATA2 | R3 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner4 | (-9.31, -4.4) | 4.487367 | top→inner4 |
| LCD_DATA3 | R4 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner6 | (-9.31, -4.4) | 5.287367 | top→inner6 |
| LCD_HSYNC | R5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-3.6, -8.38) | 4.357367 | top→inner6 |
| LCD_AC_BIAS_EN | R6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-2.8, -8.38) | 4.357367 | top→inner6 |
| GPMC_ADVn_ALE | R7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-2, -8.38) | 4.357367 | top→inner6 |
| GPMC_AD2 | R8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-1.2, -8.38) | 4.357367 | top→inner6 |
| GPMC_AD6 | R9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-0.4, -8.38) | 4.357367 | top→inner6 |
| GPMC_AD13 | R12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (2, -8.38) | 4.357367 | top→inner6 |
| GPMC_A0 | R13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (2.8, -8.38) | 4.357367 | top→inner6 |
| GPMC_A4 | R14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (3.6, -8.38) | 4.357367 | top→inner6 |
| USB1_DP | R17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -4.07874) | 3.168627 | top→inner2 |
| USB1_DM | R18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -4.4) | 3.068628 | top→inner2 |
| LCD_DATA4 | T1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, -5.2) | 2.51 | none |
| LCD_DATA5 | T2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -5.2) | 3.687367 | top→inner2 |
| LCD_DATA6 | T3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-5.2, -8.38) | 3.557367 | top→inner4 |
| LCD_DATA7 | T4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-4.4, -8.38) | 3.557367 | top→inner4 |
| LCD_DATA15 | T5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-3.6, -8.38) | 3.557367 | top→inner4 |
| GPMC_BEn0_CLE | T6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2.8, -8.38) | 3.557367 | top→inner4 |
| GPMC_OEn_REn | T7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD3 | T8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-1.2, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD7 | T9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-0.4, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD9 | T10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (0.4, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD10 | T11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (1.2, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD12 | T12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2, -8.38) | 3.557367 | top→inner4 |
| GPMC_CSn3 | T13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2.8, -8.38) | 3.557367 | top→inner4 |
| GPMC_A3 | T14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (3.6, -8.38) | 3.557367 | top→inner4 |
| GPMC_A7 | T15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (4.4, -8.38) | 3.557367 | top→inner4 |
| GPMC_A10 | T16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (5.2, -8.38) | 3.557367 | top→inner4 |
| GPMC_WAIT0 | T17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -5.2) | 2.847367 | top→inner2 |
| USB1_VBUS | T18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -5.2) | 1.67 | none |
| LCD_DATA8 | U1 | left | (-1, 0) | (-1, 0) | (-1, 0) | top | (-9.31, -6) | 2.51 | none |
| LCD_DATA9 | U2 | left | (-1, 0) | (-1, 0) | (-0.707107, -0.707107) | inner2 | (-9.31, -6) | 3.687367 | top→inner2 |
| LCD_DATA10 | U3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-5.2, -8.38) | 2.757367 | top→inner2 |
| LCD_DATA11 | U4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-4.4, -8.38) | 2.757367 | top→inner2 |
| LCD_VSYNC | U5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-3.6, -8.38) | 2.757367 | top→inner2 |
| GPMC_WEn | U6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2.8, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD0 | U7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD4 | U8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-1.2, -8.38) | 2.757367 | top→inner2 |
| GPMC_CSn1 | U9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-0.4, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD8 | U10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (0.4, -8.38) | 2.757367 | top→inner2 |
| XTALOUT | U11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (1.2, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD11 | U12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD15 | U13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2.8, -8.38) | 2.757367 | top→inner2 |
| GPMC_A2 | U14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (3.6, -8.38) | 2.757367 | top→inner2 |
| GPMC_A6 | U15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (4.4, -8.38) | 2.757367 | top→inner2 |
| GPMC_A9 | U16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (5.2, -8.38) | 2.757367 | top→inner2 |
| GPMC_WPn | U17 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (6, -8.38) | 2.757367 | top→inner2 |
| GPMC_BEn1 | U18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -6) | 1.67 | none |
| LCD_DATA12 | V2 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-6, -8.38) | 1.58 | none |
| LCD_DATA13 | V3 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-5.2, -8.38) | 1.58 | none |
| LCD_DATA14 | V4 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-4.4, -8.38) | 1.58 | none |
| LCD_PCLK | V5 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-3.6, -8.38) | 1.58 | none |
| GPMC_CSn0 | V6 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2.8, -8.38) | 1.58 | none |
| GPMC_AD1 | V7 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2, -8.38) | 1.58 | none |
| GPMC_AD5 | V8 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-1.2, -8.38) | 1.58 | none |
| GPMC_CSn2 | V9 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-0.4, -8.38) | 1.58 | none |
| XTALIN | V10 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (0.4, -8.38) | 1.58 | none |
| GPMC_CLK | V12 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2, -8.38) | 1.58 | none |
| GPMC_AD14 | V13 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2.8, -8.38) | 1.58 | none |
| GPMC_A1 | V14 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (3.6, -8.38) | 1.58 | none |
| GPMC_A5 | V15 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (4.4, -8.38) | 1.58 | none |
| GPMC_A8 | V16 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (5.2, -8.38) | 1.58 | none |
| GPMC_A11 | V17 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (6, -8.38) | 1.58 | none |
## ddr_top
23.48 × 17.94 mm local boundary, x=[-15.01, 8.47], y=[-8.38, 9.56]. Package padding (left/right/top/bottom): 7.51/0.97/2.06/0.88 mm; 10 layers (top → inner1 → inner2 → inner3 → inner4 → inner5 → inner6 → inner7 → inner8 → bottom). 201 external signal exits. Fixed local supply and capacitor routes do not terminate at the fanout boundary and are excluded.
### DDR exit distribution
| Side | Copper layer | Signals |
| --- | --- | --- |
| top | top | DDR_A5, DDR_A9, DDR_BA1, DDR_CASn, DDR_ODT, DDR_A1, DDR_D8, DDR_D9, DDR_D15, DDR_D2 |
| top | inner2 | DDR_WEn, DDR_A3, DDR_BA0, DDR_A11, DDR_A0, DDR_A10, DDR_DQM1, DDR_VTP, DDR_VREF, DDR_D0, DDR_D1, DDR_D3, DDR_DQS0, DDR_DQSn0 |
| top | inner4 | DDR_BA2, DDR_A7, DDR_A12, DDR_A2, DDR_CSn0, DDR_A13, DDR_A14, DDR_DQS1, DDR_DQSn1, DDR_D13, DDR_D14, DDR_DQM0, DDR_D6, DDR_D7 |
| top | inner6 | DDR_A4, DDR_CKn, DDR_CK, DDR_A15, DDR_A8, DDR_A6, DDR_RESETn, DDR_CKE, DDR_RASn, DDR_D10, DDR_D11, DDR_D12, DDR_D4, DDR_D5 |
### All signal exits
| Signal | Ball | Side | Outward (dx, dy) | Final tangent (dx, dy) | Source escape (dx, dy) | Layer | Exit (x, y) mm | Planar mm | Logical vias |
| --- | --- | --- | --- | --- | --- | --- | --- | ---: | --- |
| RTC_XTALOUT | A4 | top | (0, 1) | (0, 1) | (0, 1) | top | (-4.4, 9.56) | 2.76 | none |
| RTC_XTALIN | A6 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2.8, 9.56) | 2.76 | none |
| AIN3 | A7 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2, 9.56) | 2.76 | none |
| AIN6 | A8 | top | (0, 1) | (0, 1) | (0, 1) | top | (-1.2, 9.56) | 2.76 | none |
| VREFN | A9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.4, 9.56) | 2.76 | none |
| WARMRSTn | A10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.4, 9.56) | 2.76 | none |
| TDO | A11 | top | (0, 1) | (0, 1) | (0, 1) | top | (1.2, 9.56) | 2.76 | none |
| TCK | A12 | top | (0, 1) | (0, 1) | (0, 1) | top | (2, 9.56) | 2.76 | none |
| MCASP0_ACLKX | A13 | top | (0, 1) | (0, 1) | (0, 1) | top | (2.8, 9.56) | 2.76 | none |
| MCASP0_AHCLKX | A14 | top | (0, 1) | (0, 1) | (0, 1) | top | (3.6, 9.56) | 2.76 | none |
| XDMA_EVENT_INTR0 | A15 | top | (0, 1) | (0, 1) | (0, 1) | top | (4.4, 9.56) | 2.76 | none |
| SPI0_CS0 | A16 | top | (0, 1) | (0, 1) | (0, 1) | top | (5.2, 9.56) | 2.76 | none |
| SPI0_SCLK | A17 | top | (0, 1) | (0, 1) | (0, 1) | top | (6, 9.56) | 2.76 | none |
| DDR_A5 | B1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-8.36, 9.56) | 5.000968 | none |
| DDR_WEn | B2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-8.7664, 9.56) | 6.544011 | top→inner2 |
| DDR_BA2 | B3 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-8.36, 9.56) | 6.137611 | top→inner4 |
| RTC_PWRONRSTn | B5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-3.6, 9.56) | 3.937367 | top→inner2 |
| AIN0 | B6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2.8, 9.56) | 3.937367 | top→inner2 |
| AIN2 | B7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2, 9.56) | 3.937367 | top→inner2 |
| AIN5 | B8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-1.2, 9.56) | 3.937367 | top→inner2 |
| VREFP | B9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.07874, 9.56) | 3.69307 | none |
| TRSTn | B10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.72126, 9.56) | 3.69307 | none |
| TDI | B11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (1.2, 9.56) | 3.937367 | top→inner2 |
| MCASP0_ACLKR | B12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2, 9.56) | 3.937367 | top→inner2 |
| MCASP0_FSX | B13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2.8, 9.56) | 3.937367 | top→inner2 |
| EMU1 | B14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (3.6, 9.56) | 3.937367 | top→inner2 |
| PWRONRSTn | B15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (4.4, 9.56) | 3.937367 | top→inner2 |
| SPI0_D1 | B16 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (5.2, 9.56) | 3.937367 | top→inner2 |
| SPI0_D0 | B17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 6) | 2.847367 | top→inner2 |
| EXTINTn | B18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 6) | 1.67 | none |
| DDR_A9 | C1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-8.7664, 9.56) | 6.207368 | none |
| DDR_A4 | C2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-8.7664, 9.56) | 7.344011 | top→inner6 |
| DDR_A3 | C3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-9.1728, 9.56) | 8.550411 | top→inner2 |
| DDR_BA0 | C4 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-8.36, 9.56) | 7.735737 | top→inner2 |
| EXT_WAKEUP | C5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-3.6, 9.56) | 4.737367 | top→inner4 |
| PMIC_POWER_EN | C6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-2.8, 9.56) | 4.737367 | top→inner4 |
| AIN1 | C7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-2, 9.56) | 4.737367 | top→inner4 |
| AIN4 | C8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-1.2, 9.56) | 4.737367 | top→inner4 |
| AIN7 | C9 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-0.4, 9.56) | 4.737367 | top→inner4 |
| TMS | C11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (1.2, 9.56) | 4.737367 | top→inner4 |
| MCASP0_AHCLKR | C12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (2, 9.56) | 4.737367 | top→inner4 |
| MCASP0_FSR | C13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (2.8, 9.56) | 4.737367 | top→inner4 |
| EMU0 | C14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (3.6, 9.56) | 4.737367 | top→inner4 |
| SPI0_CS1 | C15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (4.4, 9.56) | 4.737367 | top→inner4 |
| I2C0_SCL | C16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 5.2) | 3.647367 | top→inner4 |
| I2C0_SDA | C17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 5.2) | 2.847367 | top→inner2 |
| ECAP0_IN_PWM0_OUT | C18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 5.2) | 1.67 | none |
| DDR_CKn | D1 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-9.5792, 9.56) | 8.824906 | top→inner6 |
| DDR_CK | D2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-9.1728, 9.56) | 8.885209 | top→inner6 |
| DDR_A15 | D3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-9.9856, 9.56) | 10.963211 | top→inner6 |
| DDR_A8 | D4 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (-8.36, 9.56) | 9.14402 | top→inner6 |
| DDR_A6 | D5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (-12.8304, 9.56) | 27.406137 | top→inner6 |
| MCASP0_AXR0 | D12 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (2, 9.56) | 5.537367 | top→inner6 |
| MCASP0_AXR1 | D13 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (2.8, 9.56) | 5.537367 | top→inner6 |
| XDMA_EVENT_INTR1 | D14 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (3.6, 9.56) | 5.537367 | top→inner6 |
| UART1_TXD | D15 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (4.4, 9.56) | 5.537367 | top→inner6 |
| UART1_RXD | D16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 4.4) | 3.647367 | top→inner4 |
| UART1_RTSn | D17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 4.4) | 2.847367 | top→inner2 |
| UART1_CTSn | D18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 4.4) | 1.67 | none |
| DDR_BA1 | E1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-9.1728, 9.56) | 8.213768 | none |
| DDR_A7 | E2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-9.5792, 9.56) | 9.756811 | top→inner4 |
| DDR_A12 | E3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-9.1728, 9.56) | 10.148537 | top→inner4 |
| DDR_A2 | E4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-8.7664, 9.56) | 10.542137 | top→inner4 |
| UART0_RXD | E15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 3.6) | 4.447367 | top→inner6 |
| UART0_TXD | E16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 3.6) | 3.647367 | top→inner4 |
| UART0_RTSn | E17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 3.6) | 2.847367 | top→inner2 |
| UART0_CTSn | E18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 3.6) | 1.67 | none |
| DDR_CASn | F1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-9.5792, 9.56) | 9.420168 | none |
| DDR_A11 | F2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-9.9856, 9.56) | 10.963211 | top→inner2 |
| DDR_A0 | F3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-9.5792, 9.56) | 11.354937 | top→inner2 |
| DDR_A10 | F4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-10.392, 9.56) | 13.769611 | top→inner2 |
| USB1_DRVVBUS | F15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 2.8) | 4.447367 | top→inner6 |
| USB0_DRVVBUS | F16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 2.8) | 3.647367 | top→inner4 |
| MMC0_DAT3 | F17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 2.8) | 2.847367 | top→inner2 |
| MMC0_DAT2 | F18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 2.8) | 1.67 | none |
| DDR_ODT | G1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-9.9856, 9.56) | 10.626568 | none |
| DDR_RESETn | G2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-10.7984, 9.56) | 12.576011 | top→inner6 |
| DDR_CKE | G3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-10.392, 9.56) | 12.967737 | top→inner6 |
| DDR_RASn | G4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-11.2048, 9.56) | 15.382411 | top→inner6 |
| MMC0_DAT1 | G15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 2) | 4.447367 | top→inner6 |
| MMC0_DAT0 | G16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 2) | 3.647367 | top→inner4 |
| MMC0_CLK | G17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 2) | 2.847367 | top→inner2 |
| MMC0_CMD | G18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 2) | 1.67 | none |
| DDR_A1 | H1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-10.392, 9.56) | 11.832968 | none |
| DDR_CSn0 | H2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-10.7984, 9.56) | 13.376011 | top→inner4 |
| DDR_A13 | H3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-10.392, 9.56) | 13.767737 | top→inner4 |
| DDR_A14 | H4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-9.9856, 9.56) | 14.161337 | top→inner4 |
| MII1_COL | H16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 1.2) | 3.647367 | top→inner4 |
| MII1_CRS | H17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 1.2) | 2.847367 | top→inner2 |
| RMII1_REF_CLK | H18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 1.2) | 1.67 | none |
| DDR_D8 | J1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-10.7984, 9.56) | 13.039368 | none |
| DDR_DQM1 | J2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-11.2048, 9.56) | 14.582411 | top→inner2 |
| DDR_VTP | J3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-10.7984, 9.56) | 14.974137 | top→inner2 |
| DDR_VREF | J4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-11.6112, 9.56) | 17.388811 | top→inner2 |
| MII1_RX_ER | J15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, 0.4) | 4.447367 | top→inner6 |
| MII1_TX_EN | J16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, 0.4) | 3.647367 | top→inner4 |
| MII1_RX_DV | J17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 0.4) | 2.847367 | top→inner2 |
| MII1_TXD3 | J18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 0.4) | 1.67 | none |
| DDR_D9 | K1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-11.2048, 9.56) | 14.245768 | none |
| DDR_D10 | K2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-12.0176, 9.56) | 16.195211 | top→inner6 |
| DDR_D11 | K3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-12.424, 9.56) | 18.201611 | top→inner6 |
| DDR_D12 | K4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-11.6112, 9.56) | 17.386937 | top→inner6 |
| MII1_TXD2 | K15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -0.4) | 4.447367 | top→inner6 |
| MII1_TXD1 | K16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -0.4) | 3.647367 | top→inner4 |
| MII1_TXD0 | K17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -0.4) | 2.847367 | top→inner2 |
| MII1_TX_CLK | K18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -0.4) | 1.67 | none |
| DDR_DQS1 | L1 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-12.424, 9.56) | 17.269706 | top→inner4 |
| DDR_DQSn1 | L2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-12.0176, 9.56) | 17.330009 | top→inner4 |
| DDR_D13 | L3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-11.6112, 9.56) | 17.386937 | top→inner4 |
| DDR_D14 | L4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-11.2048, 9.56) | 17.780537 | top→inner4 |
| MII1_RXD1 | L15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -1.2) | 4.447367 | top→inner6 |
| MII1_RXD2 | L16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -1.2) | 3.647367 | top→inner4 |
| MII1_RXD3 | L17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -1.2) | 2.847367 | top→inner2 |
| MII1_RX_CLK | L18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -1.2) | 1.67 | none |
| DDR_D15 | M1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-11.6112, 9.56) | 16.252168 | none |
| DDR_DQM0 | M2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-12.8304, 9.56) | 18.608011 | top→inner4 |
| DDR_D0 | M3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-12.424, 9.56) | 19.001611 | top→inner2 |
| DDR_D1 | M4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-12.0176, 9.56) | 19.393337 | top→inner2 |
| USB0_CE | M15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -2) | 4.447367 | top→inner6 |
| MII1_RXD0 | M16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -2) | 3.647367 | top→inner4 |
| MDIO | M17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2) | 2.847367 | top→inner2 |
| MDC | M18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -2) | 1.67 | none |
| DDR_D2 | N1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-12.0176, 9.56) | 17.458568 | none |
| DDR_D3 | N2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-12.8304, 9.56) | 19.408011 | top→inner2 |
| DDR_D4 | N3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-13.2368, 9.56) | 20.614411 | top→inner6 |
| DDR_D5 | N4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-13.6432, 9.56) | 22.620811 | top→inner6 |
| USB0_DP | N17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2.47874) | 3.168627 | top→inner2 |
| USB0_DM | N18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2.8) | 3.068628 | top→inner2 |
| DDR_DQS0 | P1 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-13.6432, 9.56) | 20.888906 | top→inner2 |
| DDR_DQSn0 | P2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-13.2368, 9.56) | 20.949209 | top→inner2 |
| DDR_D6 | P3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-13.6432, 9.56) | 21.820811 | top→inner4 |
| DDR_D7 | P4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-13.2368, 9.56) | 22.212537 | top→inner4 |
| USB0_VBUS | P15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -3.6) | 4.447367 | top→inner6 |
| USB0_ID | P16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -3.6) | 3.647367 | top→inner4 |
| USB1_ID | P17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -3.6) | 2.847367 | top→inner2 |
| USB1_CE | P18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -3.6) | 1.67 | none |
| LCD_DATA0 | R1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-12.424, 9.56) | 19.464968 | none |
| LCD_DATA1 | R2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-14.0496, 9.56) | 22.267935 | top→inner2 |
| LCD_DATA2 | R3 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner4 | (-14.0496, 9.56) | 23.067935 | top→inner4 |
| LCD_DATA3 | R4 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner6 | (-14.0496, 9.56) | 23.867935 | top→inner6 |
| LCD_HSYNC | R5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-3.6, -8.38) | 4.357367 | top→inner6 |
| LCD_AC_BIAS_EN | R6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-2.8, -8.38) | 4.357367 | top→inner6 |
| GPMC_ADVn_ALE | R7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-2, -8.38) | 4.357367 | top→inner6 |
| GPMC_AD2 | R8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-1.2, -8.38) | 4.357367 | top→inner6 |
| GPMC_AD6 | R9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-0.4, -8.38) | 4.357367 | top→inner6 |
| GPMC_AD13 | R12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (2, -8.38) | 4.357367 | top→inner6 |
| GPMC_A0 | R13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (2.8, -8.38) | 4.357367 | top→inner6 |
| GPMC_A4 | R14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (3.6, -8.38) | 4.357367 | top→inner6 |
| USB1_DP | R17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -4.07874) | 3.168627 | top→inner2 |
| USB1_DM | R18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -4.4) | 3.068628 | top→inner2 |
| LCD_DATA4 | T1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-12.8304, 9.56) | 20.671368 | none |
| LCD_DATA5 | T2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-14.456, 9.56) | 23.474335 | top→inner2 |
| LCD_DATA6 | T3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-5.2, -8.38) | 3.557367 | top→inner4 |
| LCD_DATA7 | T4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-4.4, -8.38) | 3.557367 | top→inner4 |
| LCD_DATA15 | T5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-3.6, -8.38) | 3.557367 | top→inner4 |
| GPMC_BEn0_CLE | T6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2.8, -8.38) | 3.557367 | top→inner4 |
| GPMC_OEn_REn | T7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD3 | T8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-1.2, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD7 | T9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-0.4, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD9 | T10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (0.4, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD10 | T11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (1.2, -8.38) | 3.557367 | top→inner4 |
| GPMC_AD12 | T12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2, -8.38) | 3.557367 | top→inner4 |
| GPMC_CSn3 | T13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2.8, -8.38) | 3.557367 | top→inner4 |
| GPMC_A3 | T14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (3.6, -8.38) | 3.557367 | top→inner4 |
| GPMC_A7 | T15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (4.4, -8.38) | 3.557367 | top→inner4 |
| GPMC_A10 | T16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (5.2, -8.38) | 3.557367 | top→inner4 |
| GPMC_WAIT0 | T17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -5.2) | 2.847367 | top→inner2 |
| USB1_VBUS | T18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -5.2) | 1.67 | none |
| LCD_DATA8 | U1 | top | (0, 1) | (0, 1) | (-1, 0) | top | (-13.2368, 9.56) | 21.877768 | none |
| LCD_DATA9 | U2 | top | (0, 1) | (0, 1) | (-0.707107, -0.707107) | inner2 | (-14.8624, 9.56) | 24.680735 | top→inner2 |
| LCD_DATA10 | U3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-5.2, -8.38) | 2.757367 | top→inner2 |
| LCD_DATA11 | U4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-4.4, -8.38) | 2.757367 | top→inner2 |
| LCD_VSYNC | U5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-3.6, -8.38) | 2.757367 | top→inner2 |
| GPMC_WEn | U6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2.8, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD0 | U7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD4 | U8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-1.2, -8.38) | 2.757367 | top→inner2 |
| GPMC_CSn1 | U9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-0.4, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD8 | U10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (0.4, -8.38) | 2.757367 | top→inner2 |
| XTALOUT | U11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (1.2, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD11 | U12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2, -8.38) | 2.757367 | top→inner2 |
| GPMC_AD15 | U13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2.8, -8.38) | 2.757367 | top→inner2 |
| GPMC_A2 | U14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (3.6, -8.38) | 2.757367 | top→inner2 |
| GPMC_A6 | U15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (4.4, -8.38) | 2.757367 | top→inner2 |
| GPMC_A9 | U16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (5.2, -8.38) | 2.757367 | top→inner2 |
| GPMC_WPn | U17 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (6, -8.38) | 2.757367 | top→inner2 |
| GPMC_BEn1 | U18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -6) | 1.67 | none |
| LCD_DATA12 | V2 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-6, -8.38) | 1.58 | none |
| LCD_DATA13 | V3 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-5.2, -8.38) | 1.58 | none |
| LCD_DATA14 | V4 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-4.4, -8.38) | 1.58 | none |
| LCD_PCLK | V5 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-3.6, -8.38) | 1.58 | none |
| GPMC_CSn0 | V6 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2.8, -8.38) | 1.58 | none |
| GPMC_AD1 | V7 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2, -8.38) | 1.58 | none |
| GPMC_AD5 | V8 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-1.2, -8.38) | 1.58 | none |
| GPMC_CSn2 | V9 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-0.4, -8.38) | 1.58 | none |
| XTALIN | V10 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (0.4, -8.38) | 1.58 | none |
| GPMC_CLK | V12 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2, -8.38) | 1.58 | none |
| GPMC_AD14 | V13 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2.8, -8.38) | 1.58 | none |
| GPMC_A1 | V14 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (3.6, -8.38) | 1.58 | none |
| GPMC_A5 | V15 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (4.4, -8.38) | 1.58 | none |
| GPMC_A8 | V16 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (5.2, -8.38) | 1.58 | none |
| GPMC_A11 | V17 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (6, -8.38) | 1.58 | none |
## ddr_bottom
23.48 × 21.33 mm local boundary, x=[-15.01, 8.47], y=[-11.97, 9.36]. Package padding (left/right/top/bottom): 7.51/0.97/1.86/4.47 mm; 10 layers (top → inner1 → inner2 → inner3 → inner4 → inner5 → inner6 → inner7 → inner8 → bottom). 201 external signal exits. Fixed local supply and capacitor routes do not terminate at the fanout boundary and are excluded.
### DDR exit distribution
| Side | Copper layer | Signals |
| --- | --- | --- |
| bottom | top | DDR_A5, DDR_A9, DDR_BA1, DDR_CASn, DDR_ODT, DDR_A1, DDR_D8, DDR_D9, DDR_D15, DDR_D2 |
| bottom | inner2 | DDR_WEn, DDR_A3, DDR_BA0, DDR_A11, DDR_A0, DDR_A10, DDR_DQM1, DDR_VTP, DDR_VREF, DDR_D0, DDR_D1, DDR_D3, DDR_DQS0, DDR_DQSn0 |
| bottom | inner4 | DDR_BA2, DDR_A7, DDR_A12, DDR_A2, DDR_CSn0, DDR_A13, DDR_A14, DDR_DQS1, DDR_DQSn1, DDR_D13, DDR_D14, DDR_DQM0, DDR_D6, DDR_D7 |
| bottom | inner6 | DDR_A4, DDR_CKn, DDR_CK, DDR_A15, DDR_A8, DDR_A6, DDR_RESETn, DDR_CKE, DDR_RASn, DDR_D10, DDR_D11, DDR_D12, DDR_D4, DDR_D5 |
### All signal exits
| Signal | Ball | Side | Outward (dx, dy) | Final tangent (dx, dy) | Source escape (dx, dy) | Layer | Exit (x, y) mm | Planar mm | Logical vias |
| --- | --- | --- | --- | --- | --- | --- | --- | ---: | --- |
| RTC_XTALOUT | A4 | top | (0, 1) | (0, 1) | (0, 1) | top | (-4.4, 9.36) | 2.56 | none |
| RTC_XTALIN | A6 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2.8, 9.36) | 2.56 | none |
| AIN3 | A7 | top | (0, 1) | (0, 1) | (0, 1) | top | (-2, 9.36) | 2.56 | none |
| AIN6 | A8 | top | (0, 1) | (0, 1) | (0, 1) | top | (-1.2, 9.36) | 2.56 | none |
| VREFN | A9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.4, 9.36) | 2.56 | none |
| WARMRSTn | A10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.4, 9.36) | 2.56 | none |
| TDO | A11 | top | (0, 1) | (0, 1) | (0, 1) | top | (1.2, 9.36) | 2.56 | none |
| TCK | A12 | top | (0, 1) | (0, 1) | (0, 1) | top | (2, 9.36) | 2.56 | none |
| MCASP0_ACLKX | A13 | top | (0, 1) | (0, 1) | (0, 1) | top | (2.8, 9.36) | 2.56 | none |
| MCASP0_AHCLKX | A14 | top | (0, 1) | (0, 1) | (0, 1) | top | (3.6, 9.36) | 2.56 | none |
| XDMA_EVENT_INTR0 | A15 | top | (0, 1) | (0, 1) | (0, 1) | top | (4.4, 9.36) | 2.56 | none |
| SPI0_CS0 | A16 | top | (0, 1) | (0, 1) | (0, 1) | top | (5.2, 9.36) | 2.56 | none |
| SPI0_SCLK | A17 | top | (0, 1) | (0, 1) | (0, 1) | top | (6, 9.36) | 2.56 | none |
| DDR_A5 | B1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-13.2268, -11.97) | 24.277768 | none |
| DDR_WEn | B2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-14.446, -11.97) | 26.633611 | top→inner2 |
| DDR_BA2 | B3 | bottom | (0, -1) | (0, -1) | (-0.707107, 0.707107) | inner4 | (-14.0396, -11.97) | 27.827211 | top→inner4 |
| RTC_PWRONRSTn | B5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-3.6, 9.36) | 3.737367 | top→inner2 |
| AIN0 | B6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2.8, 9.36) | 3.737367 | top→inner2 |
| AIN2 | B7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-2, 9.36) | 3.737367 | top→inner2 |
| AIN5 | B8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner2 | (-1.2, 9.36) | 3.737367 | top→inner2 |
| VREFP | B9 | top | (0, 1) | (0, 1) | (0, 1) | top | (-0.07874, 9.36) | 3.49307 | none |
| TRSTn | B10 | top | (0, 1) | (0, 1) | (0, 1) | top | (0.72126, 9.36) | 3.49307 | none |
| TDI | B11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (1.2, 9.36) | 3.737367 | top→inner2 |
| MCASP0_ACLKR | B12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2, 9.36) | 3.737367 | top→inner2 |
| MCASP0_FSX | B13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (2.8, 9.36) | 3.737367 | top→inner2 |
| EMU1 | B14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (3.6, 9.36) | 3.737367 | top→inner2 |
| PWRONRSTn | B15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (4.4, 9.36) | 3.737367 | top→inner2 |
| SPI0_D1 | B16 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner2 | (5.2, 9.36) | 3.737367 | top→inner2 |
| SPI0_D0 | B17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 6) | 2.847367 | top→inner2 |
| EXTINTn | B18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 6) | 1.67 | none |
| DDR_A9 | C1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-12.8204, -11.97) | 23.071368 | none |
| DDR_A4 | C2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-13.6332, -11.97) | 25.020811 | top→inner6 |
| DDR_A3 | C3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-14.0396, -11.97) | 26.227211 | top→inner2 |
| DDR_BA0 | C4 | bottom | (0, -1) | (0, -1) | (-0.707107, 0.707107) | inner2 | (-14.8524, -11.97) | 35.036537 | top→inner2 |
| EXT_WAKEUP | C5 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-3.6, 9.36) | 4.537367 | top→inner4 |
| PMIC_POWER_EN | C6 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-2.8, 9.36) | 4.537367 | top→inner4 |
| AIN1 | C7 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-2, 9.36) | 4.537367 | top→inner4 |
| AIN4 | C8 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-1.2, 9.36) | 4.537367 | top→inner4 |
| AIN7 | C9 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner4 | (-0.4, 9.36) | 4.537367 | top→inner4 |
| TMS | C11 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (1.2, 9.36) | 4.537367 | top→inner4 |
| MCASP0_AHCLKR | C12 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (2, 9.36) | 4.537367 | top→inner4 |
| MCASP0_FSR | C13 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (2.8, 9.36) | 4.537367 | top→inner4 |
| EMU0 | C14 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (3.6, 9.36) | 4.537367 | top→inner4 |
| SPI0_CS1 | C15 | top | (0, 1) | (0, 1) | (0.707107, 0.707107) | inner4 | (4.4, 9.36) | 4.537367 | top→inner4 |
| I2C0_SCL | C16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 5.2) | 3.647367 | top→inner4 |
| I2C0_SDA | C17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 5.2) | 2.847367 | top→inner2 |
| ECAP0_IN_PWM0_OUT | C18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 5.2) | 1.67 | none |
| DDR_CKn | D1 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-12.8204, -11.97) | 24.677352 | top→inner6 |
| DDR_CK | D2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-13.2268, -11.97) | 24.612537 | top→inner6 |
| DDR_A15 | D3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-12.414, -11.97) | 23.001611 | top→inner6 |
| DDR_A8 | D4 | bottom | (0, -1) | (0, -1) | (-0.707107, 0.707107) | inner6 | (-14.0396, -11.97) | 35.63362 | top→inner6 |
| DDR_A6 | D5 | bottom | (0, -1) | (0, -1) | (-0.707107, 0.707107) | inner6 | (-9.5692, -11.97) | 22.554937 | top→inner6 |
| MCASP0_AXR0 | D12 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (2, 9.36) | 5.337367 | top→inner6 |
| MCASP0_AXR1 | D13 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (2.8, 9.36) | 5.337367 | top→inner6 |
| XDMA_EVENT_INTR1 | D14 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (3.6, 9.36) | 5.337367 | top→inner6 |
| UART1_TXD | D15 | top | (0, 1) | (0, 1) | (-0.707107, 0.707107) | inner6 | (4.4, 9.36) | 5.337367 | top→inner6 |
| UART1_RXD | D16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 4.4) | 3.647367 | top→inner4 |
| UART1_RTSn | D17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 4.4) | 2.847367 | top→inner2 |
| UART1_CTSn | D18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 4.4) | 1.67 | none |
| DDR_BA1 | E1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-12.414, -11.97) | 21.064968 | none |
| DDR_A7 | E2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-12.8204, -11.97) | 22.608011 | top→inner4 |
| DDR_A12 | E3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-13.2268, -11.97) | 25.412537 | top→inner4 |
| DDR_A2 | E4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-13.6332, -11.97) | 28.218937 | top→inner4 |
| UART0_RXD | E15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 3.6) | 4.447367 | top→inner6 |
| UART0_TXD | E16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 3.6) | 3.647367 | top→inner4 |
| UART0_RTSn | E17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 3.6) | 2.847367 | top→inner2 |
| UART0_CTSn | E18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 3.6) | 1.67 | none |
| DDR_CASn | F1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-12.0076, -11.97) | 19.858568 | none |
| DDR_A11 | F2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-13.2268, -11.97) | 22.214411 | top→inner2 |
| DDR_A0 | F3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-13.6332, -11.97) | 25.018937 | top→inner2 |
| DDR_A10 | F4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-12.8204, -11.97) | 22.608011 | top→inner2 |
| USB1_DRVVBUS | F15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 2.8) | 4.447367 | top→inner6 |
| USB0_DRVVBUS | F16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 2.8) | 3.647367 | top→inner4 |
| MMC0_DAT3 | F17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 2.8) | 2.847367 | top→inner2 |
| MMC0_DAT2 | F18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 2.8) | 1.67 | none |
| DDR_ODT | G1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-11.6012, -11.97) | 18.652168 | none |
| DDR_RESETn | G2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-11.6012, -11.97) | 19.788811 | top→inner6 |
| DDR_CKE | G3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-12.0076, -11.97) | 22.593337 | top→inner6 |
| DDR_RASn | G4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-11.1948, -11.97) | 20.182411 | top→inner6 |
| MMC0_DAT1 | G15 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner6 | (8.47, 2) | 4.447367 | top→inner6 |
| MMC0_DAT0 | G16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 2) | 3.647367 | top→inner4 |
| MMC0_CLK | G17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 2) | 2.847367 | top→inner2 |
| MMC0_CMD | G18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 2) | 1.67 | none |
| DDR_A1 | H1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-11.1948, -11.97) | 17.445768 | none |
| DDR_CSn0 | H2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-11.6012, -11.97) | 18.988811 | top→inner4 |
| DDR_A13 | H3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-12.0076, -11.97) | 21.793337 | top→inner4 |
| DDR_A14 | H4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-12.414, -11.97) | 24.599737 | top→inner4 |
| MII1_COL | H16 | right | (1, 0) | (1, 0) | (0.707107, 0.707107) | inner4 | (8.47, 1.2) | 3.647367 | top→inner4 |
| MII1_CRS | H17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 1.2) | 2.847367 | top→inner2 |
| RMII1_REF_CLK | H18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 1.2) | 1.67 | none |
| DDR_D8 | J1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-10.7884, -11.97) | 16.239368 | none |
| DDR_DQM1 | J2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-12.0076, -11.97) | 18.595211 | top→inner2 |
| DDR_VTP | J3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-12.414, -11.97) | 21.399737 | top→inner2 |
| DDR_VREF | J4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-11.6012, -11.97) | 18.988811 | top→inner2 |
| MII1_RX_ER | J15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, 0.4) | 4.447367 | top→inner6 |
| MII1_TX_EN | J16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, 0.4) | 3.647367 | top→inner4 |
| MII1_RX_DV | J17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, 0.4) | 2.847367 | top→inner2 |
| MII1_TXD3 | J18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, 0.4) | 1.67 | none |
| DDR_D9 | K1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-10.382, -11.97) | 15.032968 | none |
| DDR_D10 | K2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-10.382, -11.97) | 16.169611 | top→inner6 |
| DDR_D11 | K3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-9.9756, -11.97) | 15.763211 | top→inner6 |
| DDR_D12 | K4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-10.7884, -11.97) | 19.774137 | top→inner6 |
| MII1_TXD2 | K15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -0.4) | 4.447367 | top→inner6 |
| MII1_TXD1 | K16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -0.4) | 3.647367 | top→inner4 |
| MII1_TXD0 | K17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -0.4) | 2.847367 | top→inner2 |
| MII1_TX_CLK | K18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -0.4) | 1.67 | none |
| DDR_DQS1 | L1 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-9.9756, -11.97) | 16.232552 | top→inner4 |
| DDR_DQSn1 | L2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-10.382, -11.97) | 16.167737 | top→inner4 |
| DDR_D13 | L3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-10.7884, -11.97) | 18.174137 | top→inner4 |
| DDR_D14 | L4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-11.1948, -11.97) | 20.980537 | top→inner4 |
| MII1_RXD1 | L15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -1.2) | 4.447367 | top→inner6 |
| MII1_RXD2 | L16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -1.2) | 3.647367 | top→inner4 |
| MII1_RXD3 | L17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -1.2) | 2.847367 | top→inner2 |
| MII1_RX_CLK | L18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -1.2) | 1.67 | none |
| DDR_D15 | M1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-9.9756, -11.97) | 13.026568 | none |
| DDR_DQM0 | M2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-9.5692, -11.97) | 13.756811 | top→inner4 |
| DDR_D0 | M3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-10.7884, -11.97) | 15.776011 | top→inner2 |
| DDR_D1 | M4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-11.1948, -11.97) | 18.580537 | top→inner2 |
| USB0_CE | M15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -2) | 4.447367 | top→inner6 |
| MII1_RXD0 | M16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -2) | 3.647367 | top→inner4 |
| MDIO | M17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2) | 2.847367 | top→inner2 |
| MDC | M18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -2) | 1.67 | none |
| DDR_D2 | N1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-9.5692, -11.97) | 11.820168 | none |
| DDR_D3 | N2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-10.382, -11.97) | 13.769611 | top→inner2 |
| DDR_D4 | N3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-9.1628, -11.97) | 13.350411 | top→inner6 |
| DDR_D5 | N4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-8.7564, -11.97) | 12.944011 | top→inner6 |
| USB0_DP | N17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2.47874) | 3.168627 | top→inner2 |
| USB0_DM | N18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -2.8) | 3.068628 | top→inner2 |
| DDR_DQS0 | P1 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-9.5692, -11.97) | 13.426152 | top→inner2 |
| DDR_DQSn0 | P2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-9.9756, -11.97) | 13.361337 | top→inner2 |
| DDR_D6 | P3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-8.7564, -11.97) | 12.144011 | top→inner4 |
| DDR_D7 | P4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-9.1628, -11.97) | 14.948537 | top→inner4 |
| USB0_VBUS | P15 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner6 | (8.47, -3.6) | 4.447367 | top→inner6 |
| USB0_ID | P16 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner4 | (8.47, -3.6) | 3.647367 | top→inner4 |
| USB1_ID | P17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -3.6) | 2.847367 | top→inner2 |
| USB1_CE | P18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -3.6) | 1.67 | none |
| LCD_DATA0 | R1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-9.1628, -11.97) | 9.813768 | none |
| LCD_DATA1 | R2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-9.1628, -11.97) | 10.991135 | top→inner2 |
| LCD_DATA2 | R3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-8.35, -11.97) | 10.978335 | top→inner4 |
| LCD_DATA3 | R4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-8.35, -11.97) | 11.778335 | top→inner6 |
| LCD_HSYNC | R5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-3.6, -11.97) | 7.947367 | top→inner6 |
| LCD_AC_BIAS_EN | R6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-2.8, -11.97) | 7.947367 | top→inner6 |
| GPMC_ADVn_ALE | R7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-2, -11.97) | 7.947367 | top→inner6 |
| GPMC_AD2 | R8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-1.2, -11.97) | 7.947367 | top→inner6 |
| GPMC_AD6 | R9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (-0.4, -11.97) | 7.947367 | top→inner6 |
| GPMC_AD13 | R12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (2, -11.97) | 7.947367 | top→inner6 |
| GPMC_A0 | R13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (2.8, -11.97) | 7.947367 | top→inner6 |
| GPMC_A4 | R14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner6 | (3.6, -11.97) | 7.947367 | top→inner6 |
| USB1_DP | R17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -4.07874) | 3.168627 | top→inner2 |
| USB1_DM | R18 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -4.4) | 3.068628 | top→inner2 |
| LCD_DATA4 | T1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-8.7564, -11.97) | 8.607368 | none |
| LCD_DATA5 | T2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-8.7564, -11.97) | 9.784735 | top→inner2 |
| LCD_DATA6 | T3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-5.2, -11.97) | 7.147367 | top→inner4 |
| LCD_DATA7 | T4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-4.4, -11.97) | 7.147367 | top→inner4 |
| LCD_DATA15 | T5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-3.6, -11.97) | 7.147367 | top→inner4 |
| GPMC_BEn0_CLE | T6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2.8, -11.97) | 7.147367 | top→inner4 |
| GPMC_OEn_REn | T7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-2, -11.97) | 7.147367 | top→inner4 |
| GPMC_AD3 | T8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-1.2, -11.97) | 7.147367 | top→inner4 |
| GPMC_AD7 | T9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (-0.4, -11.97) | 7.147367 | top→inner4 |
| GPMC_AD9 | T10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (0.4, -11.97) | 7.147367 | top→inner4 |
| GPMC_AD10 | T11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (1.2, -11.97) | 7.147367 | top→inner4 |
| GPMC_AD12 | T12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2, -11.97) | 7.147367 | top→inner4 |
| GPMC_CSn3 | T13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (2.8, -11.97) | 7.147367 | top→inner4 |
| GPMC_A3 | T14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (3.6, -11.97) | 7.147367 | top→inner4 |
| GPMC_A7 | T15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (4.4, -11.97) | 7.147367 | top→inner4 |
| GPMC_A10 | T16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner4 | (5.2, -11.97) | 7.147367 | top→inner4 |
| GPMC_WAIT0 | T17 | right | (1, 0) | (1, 0) | (0.707107, -0.707107) | inner2 | (8.47, -5.2) | 2.847367 | top→inner2 |
| USB1_VBUS | T18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -5.2) | 1.67 | none |
| LCD_DATA8 | U1 | bottom | (0, -1) | (0, -1) | (-1, 0) | top | (-8.35, -11.97) | 7.400968 | none |
| LCD_DATA9 | U2 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-8.35, -11.97) | 8.578335 | top→inner2 |
| LCD_DATA10 | U3 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-5.2, -11.97) | 6.347367 | top→inner2 |
| LCD_DATA11 | U4 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-4.4, -11.97) | 6.347367 | top→inner2 |
| LCD_VSYNC | U5 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-3.6, -11.97) | 6.347367 | top→inner2 |
| GPMC_WEn | U6 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2.8, -11.97) | 6.347367 | top→inner2 |
| GPMC_AD0 | U7 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-2, -11.97) | 6.347367 | top→inner2 |
| GPMC_AD4 | U8 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-1.2, -11.97) | 6.347367 | top→inner2 |
| GPMC_CSn1 | U9 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (-0.4, -11.97) | 6.347367 | top→inner2 |
| GPMC_AD8 | U10 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (0.4, -11.97) | 6.347367 | top→inner2 |
| XTALOUT | U11 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (1.2, -11.97) | 6.347367 | top→inner2 |
| GPMC_AD11 | U12 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2, -11.97) | 6.347367 | top→inner2 |
| GPMC_AD15 | U13 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (2.8, -11.97) | 6.347367 | top→inner2 |
| GPMC_A2 | U14 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (3.6, -11.97) | 6.347367 | top→inner2 |
| GPMC_A6 | U15 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (4.4, -11.97) | 6.347367 | top→inner2 |
| GPMC_A9 | U16 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (5.2, -11.97) | 6.347367 | top→inner2 |
| GPMC_WPn | U17 | bottom | (0, -1) | (0, -1) | (-0.707107, -0.707107) | inner2 | (6, -11.97) | 6.347367 | top→inner2 |
| GPMC_BEn1 | U18 | right | (1, 0) | (1, 0) | (1, 0) | top | (8.47, -6) | 1.67 | none |
| LCD_DATA12 | V2 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-6, -11.97) | 5.17 | none |
| LCD_DATA13 | V3 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-5.2, -11.97) | 5.17 | none |
| LCD_DATA14 | V4 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-4.4, -11.97) | 5.17 | none |
| LCD_PCLK | V5 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-3.6, -11.97) | 5.17 | none |
| GPMC_CSn0 | V6 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2.8, -11.97) | 5.17 | none |
| GPMC_AD1 | V7 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-2, -11.97) | 5.17 | none |
| GPMC_AD5 | V8 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-1.2, -11.97) | 5.17 | none |
| GPMC_CSn2 | V9 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (-0.4, -11.97) | 5.17 | none |
| XTALIN | V10 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (0.4, -11.97) | 5.17 | none |
| GPMC_CLK | V12 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2, -11.97) | 5.17 | none |
| GPMC_AD14 | V13 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (2.8, -11.97) | 5.17 | none |
| GPMC_A1 | V14 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (3.6, -11.97) | 5.17 | none |
| GPMC_A5 | V15 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (4.4, -11.97) | 5.17 | none |
| GPMC_A8 | V16 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (5.2, -11.97) | 5.17 | none |
| GPMC_A11 | V17 | bottom | (0, -1) | (0, -1) | (0, -1) | top | (6, -11.97) | 5.17 | none |
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