0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
Stars
0

scripts/check-ddr-integration-render.tsx

import { readFileSync, mkdirSync, writeFileSync } from 'node:fs'
import { resolve } from 'node:path'
import { strict as assert } from 'node:assert'
import { Fragment } from 'react'
import { RootCircuit } from '@tscircuit/core'
import { DdrMemoryAdapter, DDR_MEMORY_SIX_LAYER_MAP, type DdrMemoryPin } from '../src/ddr-memory'
const input=process.argv[2]
if(!input)throw new Error('Usage: bun scripts/check-ddr-integration-render.tsx /path/to/memory-fanout')
const base=resolve(input)
const pins=JSON.parse(readFileSync(resolve(base,'src/pin-map.json'),'utf8')) as Array<DdrMemoryPin & {x:number;y:number;radius:number}>
mkdirSync('dist/ddr-integration',{recursive:true})
for(const profile of ['bus_grouped','outward_north','outward_south','inward_north','inward_south']) {
 const paths=JSON.parse(readFileSync(resolve(base,`src/generated/${profile}.trace-paths.json`),'utf8'))
 const boundary=profile==='bus_grouped'?JSON.parse(readFileSync(resolve(base,'src/generated/bus_grouped.boundary.json'),'utf8')):undefined
 const c=new RootCircuit()
 c.add(<board width={14} height={16} layers={10} schematicDisabled allowBlindAndBuriedVias={false}>
  <DdrMemoryAdapter name="RAM" paths={paths} layerMap={profile==='bus_grouped'?DDR_MEMORY_SIX_LAYER_MAP:undefined} boundary={boundary} traceWidthMm={profile==='bus_grouped'?.1168:undefined} pins={pins} footprint={<footprint>{pins.map(p=><Fragment key={p.ball}><smtpad portHints={[`pin${p.pin}`]} pcbX={p.x} pcbY={p.y} radius={p.radius} shape="circle"/></Fragment>)}</footprint>}/>
 </board>)
 await c.renderUntilSettled()
 const json=c.getCircuitJson()
 const pads=json.filter(e=>e.type==='pcb_smtpad'),vias=json.filter(e=>e.type==='pcb_via'),traces=json.filter(e=>e.type==='pcb_trace'),exits=json.filter(e=>e.type==='pcb_breakout_point')
 assert.equal(pads.length,78);assert.equal(vias.length,profile==='bus_grouped'?52:50);assert.equal(traces.length,72);assert.equal(exits.length,72)
 for(const via of vias){assert.equal(via.outer_diameter,.4572);assert.equal(via.hole_diameter,.254);assert.equal(via.layers.length,10)}
 assert(!traces.some(t=>t.route.some(p=>p.route_type==='wire'&&!['top','inner2','inner4','bottom'].includes(p.layer))))
 for(const trace of traces) for(const point of trace.route) if(point.route_type==='wire') assert(Math.abs(point.width-(profile==='bus_grouped'?.1168:.12))<1e-10)
 assert.deepEqual(json.filter(e=>e.type.endsWith('_error')),[])
 for(const t of traces){const end=t.route.at(-1)!;assert.equal(end.route_type,'wire');assert(exits.some(e=>e.x===end.x&&e.y===end.y&&e.layer===(end as any).layer))}
 writeFileSync(`dist/ddr-integration/${profile}.circuit.json`,JSON.stringify(json,null,2)+'\n')
 console.log(`${profile}: 78 pads, 72 rendered paths/exits, ${vias.length} ten-layer vias; no emitted errors`)
}