0hmX/am3352
This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.
- Version
- 1.0.5
- License
- unset
- Stars
- 0
scripts/experiment-ddr-f8-via-relocation.ts
/** Bounded F8 barrel relocation experiment; never writes a routing candidate. */
import{readFileSync,writeFileSync,mkdirSync}from'node:fs'
import{resolve}from'node:path'
import{objectHash}from'./improve-ddr-a9-power-launches'
import{verifyDdrSystemCopper}from'./check-ddr-system-copper'
import{sharedViaApproaches}from'./plan-ddr-ram-power-via-reuse'
const dir=resolve('dist/ddr-facing-progress-45'),out=resolve('dist/ddr-f8-relocation-experiment'),read=(n:string)=>JSON.parse(readFileSync(`${dir}/${n}`,'utf8')),parent=read('candidate.circuit.json'),audit=read('ram-power-launch-audit.json'),report=read('report.json'),attempts:any[]=[],hits:any[]=[],started=Date.now()
for(const byte of[0,1]){
const row=audit.rows.find((r:any)=>r.byte===byte&&r.terminal==='VSS_F8'),e9row=audit.rows.find((r:any)=>r.byte===byte&&r.terminal==='VDDQ_E9'),target=audit.rows.find((r:any)=>r.byte===byte&&r.terminal==='VDD_G8').connectionVia,t=parent.find((e:any)=>e.type==='pcb_trace'&&e.pcb_trace_id===row.pcbTraceId),e9=parent.find((e:any)=>e.type==='pcb_trace'&&e.pcb_trace_id===e9row.pcbTraceId),old=t.route[2],pad=parent.find((e:any)=>e.type==='pcb_smtpad'&&e.pcb_smtpad_id===row.padId),rendered=parent.filter((e:any)=>e.type==='pcb_via'&&e.pcb_trace_id===t.pcb_trace_id)
if(rendered.length!==1||audit.rows.filter((r:any)=>r.connectionVia&&Math.hypot(r.connectionVia.x-old.x,r.connectionVia.y-old.y)<1e-7).length!==1)throw Error('Expected singly owned F8 barrel')
for(const dx of[.1,.15,.2,.25,.3,.35,.4])for(const dy of[-.3,-.2,-.1,0,.1,.2,.3]){
if(Date.now()-started>55000)break
const v={x:old.x+dx,y:old.y+dy},padHoleGap=Math.hypot(v.x-pad.x,v.y-pad.y)-.127-pad.radius
// Keep the through-drill separated from the actual solderable BGA pad.
if(padHoleGap<.1016-1e-8){attempts.push({byte,dx,dy,status:'own-pad-drill-gap',padHoleGap});continue}
const viaGap=Math.min(...parent.filter((e:any)=>e.type==='pcb_via'&&!rendered.includes(e)).map((e:any)=>Math.hypot(v.x-e.x,v.y-e.y)-.2286-e.outer_diameter/2))
if(viaGap<.1016-1e-8){attempts.push({byte,dx,dy,status:'other-barrel-gap',viaGap});continue}
for(const approach of sharedViaApproaches(t.route[0],v)){
const moved={...t,route:[...approach,{...old,...v}]},newRendered={...rendered[0],...v},base=parent.filter((e:any)=>e.type!=='pcb_copper_pour'&&e!==t&&e!==e9&&!rendered.includes(e)),fixed=[...base,moved,newRendered],r=verifyDdrSystemCopper(fixed,[moved],[],{},0)
if(r.errors.length||r.violations.length||!r.angles.valid||r.joinedBends.length){attempts.push({byte,dx,dy,status:'relocation-copper-blocked',padHoleGap,viaGap,errors:r.errors,blockers:r.violations.map((w:any)=>({layer:w.layer,gapMm:w.gapMm,a:w.aShape.traceId??w.aShape.join,b:w.bShape.traceId??w.bShape.join}))});continue}
const a=e9.route[0],ex=target.x-a.x,ey=target.y-a.y,vertical=ey-ex
for(let k=0;k<=20;k++){
const lead=vertical*k/20,points=[a,{x:a.x,y:a.y+lead},{x:target.x,y:a.y+lead+ex},target],route:any[]=[a]
for(const p of points.slice(1))if(Math.hypot(p.x-route.at(-1).x,p.y-route.at(-1).y)>1e-8)route.push({route_type:'wire',x:p.x,y:p.y,width:.12,layer:'top'})
const added={...e9,route},check=verifyDdrSystemCopper(fixed,[moved,added],[],{},0),pass=!check.errors.length&&!check.violations.length&&check.angles.valid&&!check.joinedBends.length
attempts.push({byte,dx,dy,lead,status:pass?'conductor-clear-pending-planes':'shared-approach-blocked',padHoleGap,viaGap,minClearanceMm:check.minClearanceMm,blockers:check.violations.map((w:any)=>({layer:w.layer,gapMm:w.gapMm,a:w.aShape.traceId??w.aShape.join,b:w.bShape.traceId??w.bShape.join}))})
if(pass){hits.push({byte,beforeTrace:t,beforeTraceSha256:objectHash(t),beforeRenderedVia:rendered[0],beforeRenderedViaSha256:objectHash(rendered[0]),afterTrace:moved,afterRenderedVia:newRendered,beforeE9:e9,afterE9:added,limits:{padHoleGap,viaGap},conductorReport:check});break}
}
if(hits.some(h=>h.byte===byte))break
}
if(hits.some(h=>h.byte===byte))break
}
}
mkdirSync(out,{recursive:true});writeFileSync(`${out}/report.json`,JSON.stringify({captureHash:report.captureHash,parentCircuitSha256:objectHash(parent),beforeWitnesses:audit.rows.filter((r:any)=>['VSS_F8','VDDQ_E9','VDD_G8'].includes(r.terminal)).map((r:any)=>{const trace=parent.find((e:any)=>e.type==='pcb_trace'&&e.pcb_trace_id===r.pcbTraceId);return{byte:r.byte,terminal:r.terminal,trace,traceSha256:objectHash(trace),renderedVias:parent.filter((e:any)=>e.type==='pcb_via'&&e.pcb_trace_id===r.pcbTraceId)}}),elapsedMs:Date.now()-started,attempts,hits,scope:'Read-only bounded relocation search. Trims unused F8 bottom tail, preserves pad, explicitly moves trace-owned rendered barrel; all actual conductor layers checked. Any conductor-clear hit still requires regenerated plane and source-pad audits before acceptance.'},null,2));console.log(JSON.stringify({elapsedMs:Date.now()-started,attempts:attempts.length,hits:hits.map(h=>({byte:h.byte,via:h.afterRenderedVia,limits:h.limits}))}))