0hmX/am3352

tests/ddr-port-identities.test.ts

import {test,expect}from'bun:test'
import {sanitizeDdrPortIdentities}from'../scripts/sanitize-ddr-port-identities'
function fixture(){return [
 {type:'source_port',source_port_id:'a'},{type:'source_port',source_port_id:'b'},{type:'source_port',source_port_id:'foreign'},
 {type:'source_trace',source_trace_id:'net',connected_source_port_ids:['a'],connected_source_net_ids:['rail']},
 {type:'source_trace',source_trace_id:'other-branch',connected_source_port_ids:['b'],connected_source_net_ids:['rail']},
 {type:'source_trace',source_trace_id:'foreign-net',connected_source_port_ids:['foreign']},
 {type:'pcb_port',pcb_port_id:'pa',source_port_id:'a',x:0,y:0,layers:['top']},
 {type:'pcb_port',pcb_port_id:'pb',source_port_id:'b',x:1,y:0,layers:['inner6']},
 {type:'pcb_port',pcb_port_id:'pf',source_port_id:'foreign',x:1,y:0,layers:['top']},
 {type:'pcb_trace',pcb_trace_id:'trace',source_trace_id:'net',connectsTo:['pa','pf'],route:[{route_type:'wire',x:0,y:0,layer:'top',width:.12,start_pcb_port_id:'pa'},{route_type:'via',x:0,y:0,from_layer:'top',to_layer:'inner6',via_diameter:.4572,via_hole_diameter:.254},{route_type:'wire',x:0,y:0,layer:'inner6',width:.12},{route_type:'wire',x:1,y:0,layer:'inner6',width:.12,end_pcb_port_id:'pf'}]},
]}
test('coincident foreign-layer endpoint cannot merge explicit nets; geometry remains intact',()=>{
 const original=fixture(),snapshot=structuredClone(original)
 const {circuit,report}=sanitizeDdrPortIdentities(original)
 expect(original).toEqual(snapshot)
 expect(report.removedAnnotations).toBe(1)
 expect(report.mismatches[0]!.reasons).toEqual(['layer-mismatch','source-net-mismatch'])
 const expected:any=structuredClone(original);delete expected.at(-1).route.at(-1).end_pcb_port_id
 expect(circuit).toEqual(expected)
 expect(sanitizeDdrPortIdentities(circuit).report.removedAnnotations).toBe(0)
})
test('explicit net membership via another source branch preserves correct metadata',()=>{
 const original:any=fixture();original.at(-1).route.at(-1).end_pcb_port_id='pb'
 expect(sanitizeDdrPortIdentities(original).circuit).toEqual(original)
 expect(sanitizeDdrPortIdentities(original).report.preservedAnnotations).toBe(2)
})
test('same-net wrong-coordinate or wrong-layer ports and invalid starts are removed',()=>{
 const original:any=fixture();original.at(-1).route.at(-1).end_pcb_port_id='pb';original.at(-1).route[0].start_pcb_port_id='absent'
 original.find((e:any)=>e.pcb_port_id==='pb').x=1.001
 let result=sanitizeDdrPortIdentities(original)
 expect(result.report.mismatches.map(m=>m.reasons)).toEqual([['unknown-pcb-port'],['coordinate-mismatch']])
 original.find((e:any)=>e.pcb_port_id==='pb').x=1;original.find((e:any)=>e.pcb_port_id==='pb').layers=['top']
 result=sanitizeDdrPortIdentities(original)
 expect(result.report.mismatches[1]!.reasons).toEqual(['layer-mismatch'])
})
test('trace annotations cannot supply missing explicit ownership',()=>{
 const original:any=fixture();original.at(-1).route.at(-1).end_pcb_port_id='pb';delete original.at(-1).source_trace_id
 expect(sanitizeDdrPortIdentities(original).report.mismatches.every(m=>m.reasons.includes('missing-explicit-source-trace'))).toBe(true)
})