0hmX/am62l-lpddr4-clean

dist/index.js

import { jsx, jsxs } from 'react/jsx-runtime';
import { Fragment } from 'react';
import { MT53E1G16D1ZW } from '@tsci/0hmX.mt53e1g16d1zw-footprint';
import { AM62L32 } from '@tsci/tscircuit.ti';

const byteConnections = Array.from({ length: 16 }, (_, bit) => ({
    bus: bit < 8 ? "DDR_BYTE0" : "DDR_BYTE1",
    memorySignal: `DQ${bit}`,
    socSignal: `DDR0_DQ${bit}`,
    trace: `DQ${bit}`,
}));
const fixedConnections = [
    ["DDR_ADDR_CTRL", "CA0", "DDR0_A0"],
    ["DDR_ADDR_CTRL", "CA1", "DDR0_A1"],
    ["DDR_ADDR_CTRL", "CA2", "DDR0_A2"],
    ["DDR_ADDR_CTRL", "CA3", "DDR0_A3"],
    ["DDR_ADDR_CTRL", "CA4", "DDR0_A4"],
    ["DDR_ADDR_CTRL", "CA5", "DDR0_A5"],
    ["DDR_ADDR_CTRL", "CS", "DDR0_CS0_n"],
    ["DDR_ADDR_CTRL", "CKE", "DDR0_CKE0"],
    ["DDR_CLOCK", "CK_t", "DDR0_CK0"],
    ["DDR_CLOCK", "CK_c", "DDR0_CK0_n"],
    ["DDR_DQS0", "DQS0_t", "DDR0_DQS0"],
    ["DDR_DQS0", "DQS0_c", "DDR0_DQS0_n"],
    ["DDR_DQS1", "DQS1_t", "DDR0_DQS1"],
    ["DDR_DQS1", "DQS1_c", "DDR0_DQS1_n"],
    ["DDR_RESET", "RESET_n", "DDR0_RESET0_n"],
];
const DDR_CONNECTIONS = [
    ...byteConnections,
    ...fixedConnections.map(([bus, memorySignal, socSignal]) => ({
        bus,
        memorySignal,
        socSignal,
        trace: memorySignal,
    })),
];
const tracesFor = (bus) => DDR_CONNECTIONS.filter((connection) => connection.bus === bus).map((connection) => connection.trace);

const Soc = () => (jsx(AM62L32, { name: "U1", footprintVariant: "fccsp_373_anb", noSchematicRepresentation: true }));
const Dram = () => (jsx(MT53E1G16D1ZW, { name: "U2", pcbRotation: 90, noSchematicRepresentation: true }));

const balls = (list) => list.trim().split(/\s+/);
const SOC_GROUND_BALLS = balls(`
  A1 A2 A4 A10 A13 A16 A19 A22 A23 B1 B5 B17 B20 B23 C12 C18 D1
  E2 E6 E8 E9 E10 E14 E15 F5 F6 F18 G7 G8 G9 G12 G15 G16 G17
  H1 H7 H14 H17 K8 K9 K15 L7 L9 L13 L16 L18 M1 M12 N7 N9 N11
  N13 N16 P9 P15 R1 R8 R13 R15 T2 T7 T8 T19 U7 U8 U10 U13 U14
  U15 U17 U20 V3 V18 V19 W9 W10 W12 W14 W15 W16 W18 Y1 Y20 Y21
  AA4 AA20 AB1 AB7 AB21 AB23 AC1 AC2 AC11 AC14 AC19 AC22 AC23
`);
const SOC_DDR_POWER_BALLS = balls("L8 M7 M8 N8 P8");
const DRAM_GROUND_BALLS = balls(`
  A3 A10 C1 C5 C8 C12 D2 D4 D9 D11 E1 E5 E8 E12 G1 G3 G5 G8 G10 G12
  J1 J3 J10 J12 K2 K4 K9 K11 N2 N4 N9 N11 P1 P3 P10 P12 T1 T3 T5 T8
  T10 T12 V1 V5 V8 V12 W2 W4 W9 W11 Y1 Y5 Y8 Y12 AB3 AB5 AB8 AB10
`);
const DRAM_VDDQ_BALLS = balls(`
  B3 B5 B8 B10 D1 D5 D8 D12 F3 F10 U3 U10 W1 W5 W8 W12 AA3 AA5 AA8 AA10
`);
const DRAM_VDD2_BALLS = balls(`
  A4 A9 F5 F8 H1 H5 H8 H12 K1 K3 K10 K12 N1 N3 N10 N12
  R1 R5 R8 R12 U5 U8 AB4 AB9
`);
const DRAM_VDD1_BALLS = balls("F1 F12 G4 G9 T4 T9 U1 U12");

const buses = [
    { name: "DDR_BYTE0", layers: ["top", "inner4"], skew: 8 },
    { name: "DDR_BYTE1", layers: ["inner5", "bottom"], skew: 14.5 },
    { name: "DDR_ADDR_CTRL", layers: ["inner6"], skew: 15 },
    { name: "DDR_CLOCK", layers: ["inner5"], skew: 0.25 },
    { name: "DDR_DQS0", layers: ["inner5"], skew: 0.25 },
    { name: "DDR_DQS1", layers: ["inner5"], skew: 0.25 },
    { name: "DDR_RESET", layers: ["inner6"] },
];
var index_circuit = () => (jsxs("board", { name: "AM62L32_LPDDR4_CLEAN", width: "42mm", height: "26mm", layers: 8, defaultTraceWidth: "0.08128mm", minTraceWidth: "0.08128mm", minTraceToPadEdgeClearance: "0.05mm", minViaEdgeToPadEdgeClearance: "0.08128mm", minViaHoleEdgeToViaHoleEdgeClearance: "0.1016mm", minViaHoleDiameter: "0.1mm", minViaPadDiameter: "0.24mm", pcbStyle: { viaHoleDiameter: "0.1mm", viaPadDiameter: "0.24mm" }, allowBlindAndBuriedVias: false, isViaInPadAllowed: false, routingDisabled: true, children: [jsx("copperpour", { layer: "inner1", connectsTo: "net.GND" }), jsx("copperpour", { layer: "inner2", connectsTo: "net.VDD_LPDDR4" }), jsx("copperpour", { layer: "inner3", connectsTo: "net.SOC_DVDD1V8" }), buses.map((bus) => (jsx(Fragment, { children: jsx("bus", { name: bus.name, connections: tracesFor(bus.name), preferredLayers: [...bus.layers], maxLengthSkew: "skew" in bus ? bus.skew : undefined }) }, bus.name))), jsx("differentialpair", { name: "DDR_CLOCK_PAIR", positiveConnection: "CK_t", negativeConnection: "CK_c", maxLengthSkew: 0.25 }), jsx("differentialpair", { name: "DDR_DQS0_PAIR", positiveConnection: "DQS0_t", negativeConnection: "DQS0_c", maxLengthSkew: 0.25 }), jsx("differentialpair", { name: "DDR_DQS1_PAIR", positiveConnection: "DQS1_t", negativeConnection: "DQS1_c", maxLengthSkew: 0.25 }), jsxs("breakout", { name: "SOC_FANOUT", pcbX: -9.5, padding: "3mm", children: [jsx(Soc, {}), jsx("trace", { name: "U1_GND_PLANE_DROP", from: ".U1 > .A1", to: "net.GND" }), jsx("trace", { name: "U1_VDD_LPDDR4_PLANE_DROP", from: ".U1 > .L8", to: "net.VDD_LPDDR4" })] }), jsxs("breakout", { name: "DRAM_FANOUT", pcbX: 9.8, pcbY: 1.81916, padding: "3mm", children: [jsx(Dram, {}), jsx("trace", { name: "U2_GND_PLANE_DROP", from: ".U2 > .A3", to: "net.GND" }), jsx("trace", { name: "U2_VDDQ_PLANE_DROP", from: ".U2 > .B3", to: "net.VDD_LPDDR4" }), jsx("trace", { name: "U2_VDD2_PLANE_DROP", from: ".U2 > .A4", to: "net.VDD_LPDDR4" }), jsx("trace", { name: "U2_VDD1_PLANE_DROP", from: ".U2 > .F1", to: "net.SOC_DVDD1V8" })] }), jsxs("group", { name: "POWER_ASSIGNMENTS", routingDisabled: true, children: [SOC_GROUND_BALLS.filter((ball) => ball !== "A1").map((ball) => (jsx(Fragment, { children: jsx("trace", { name: `U1_GND_${ball}`, from: `U1.${ball}`, to: "net.GND" }) }, `U1-GND-${ball}`))), SOC_DDR_POWER_BALLS.filter((ball) => ball !== "L8").map((ball) => (jsx(Fragment, { children: jsx("trace", { name: `U1_VDD_LPDDR4_${ball}`, from: `U1.${ball}`, to: "net.VDD_LPDDR4" }) }, `U1-VDD-${ball}`))), DRAM_GROUND_BALLS.filter((ball) => ball !== "A3").map((ball) => (jsx(Fragment, { children: jsx("trace", { name: `U2_GND_${ball}`, from: `U2.${ball}`, to: "net.GND" }) }, `U2-GND-${ball}`))), DRAM_VDDQ_BALLS.filter((ball) => ball !== "B3").map((ball) => (jsx(Fragment, { children: jsx("trace", { name: `U2_VDDQ_${ball}`, from: `U2.${ball}`, to: "net.VDD_LPDDR4" }) }, `U2-VDDQ-${ball}`))), DRAM_VDD2_BALLS.filter((ball) => ball !== "A4").map((ball) => (jsx(Fragment, { children: jsx("trace", { name: `U2_VDD2_${ball}`, from: `U2.${ball}`, to: "net.VDD_LPDDR4" }) }, `U2-VDD2-${ball}`))), DRAM_VDD1_BALLS.filter((ball) => ball !== "F1").map((ball) => (jsx(Fragment, { children: jsx("trace", { name: `U2_SOC_DVDD1V8_${ball}`, from: `U2.${ball}`, to: "net.SOC_DVDD1V8" }) }, `U2-VDD1-${ball}`)))] }), DDR_CONNECTIONS.map((connection) => (jsx(Fragment, { children: jsx("trace", { name: connection.trace, from: `U1.${connection.socSignal}`, to: `U2.${connection.memorySignal}` }) }, connection.trace))), jsx("pcbnotetext", { pcbX: 0, pcbY: 11.2, fontSize: "0.65mm", text: "AM62L32 + MT53E1G16D1ZW: 31 DDR nets with complete GND and power assignments" })] }));

export { index_circuit as default };